Adrián Núñez-Aldana

Behavioral synthesis of analog systems using two-layered design space exploration

This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. The synthesis process produces a netlist of electronic components that are selected from a component library and sized such that the overall area is minimized and the rest of the performance constraints such as power, slew-rate, bandwidth, etc. are met. The gap between system level specifications and implementations is bridged using a hierarchically-organized, design-space exploration methodology. Our methodology performs a two-layered synthesis, the first being architecture generation, and the other component synthesis and constraint transformation. For architecture generation we suggest a branch-and-bound algorithm, while component synthesis and constraint transformation use a genetic algorithm based heuristic method. Crucial to the success of our exploration methodology is a fast and accurate performance estimation engine that embeds technology process parameters, SPICE models for basic circuits and performance composition equations. We present a telecommunication application as an example to illustrate our synthesis methodology, and show that constraint-satisfying designs can be synthesized in a short time and with a reduced designer effort.

A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications

This paper presents a synthesis methodology for analog systems described using VHDL-AMS language. Synthesis produces net-lists of analog components that are selected from a library, and sized so that specified objectives (like AC response, signal to noise ratio, dynamic range, area) are optimized. The gap between abstract specifications and implementations is bridged using a two-layered methodology. The first layer is architecture generation. The second layer is component synthesis and constraint transformation. Architecture generation employs the branch-and-bound algorithm to create architectural alternatives for a system. Component synthesis and constraint transformation use a directed interval based genetic algorithm that operates on parameter ranges. The performance estimation engine embeds technology process parameters, SPICE models for basic circuits, and symbolic composition equations for basic structural configurations. The paper discusses the VHDL-AMS subset for synthesis. The subset offers the composition semantics. As a result, specifications offer sufficient insight into the system structure to allow automated architecture generation. To justify the flexibility of the methodology, the paper presents results for three case studies, a signal conditioning system, a filter, and an analog to digital converter. Experiments show that constraint-satisfying designs can be synthesized in a short time, at a low cost, and without requesting broad knowledge on analog circuits.

An analog performance estimator for improving the effectiveness of CMOS analog systems circuit synthesis

Critical to the automation of analog circuit systems is the estimation process of performance parameters which are used to guide the topology selection and circuit sizing processes. This paper presents a methodology to improve the effectiveness of the CMOS analog system circuit synthesis search process by developing an Analog Performance Estimator (APE) tool. APE is capable of accepting the design parameters of an analog circuit and determine its performance parameters along with anticipated sizes of all the circuit elements. The APE is structured as a hierarchical estimation engine containing performance models of analog circuits at various levels of abstraction.

Hierarchical constraint transformation using directed interval search for analog system synthesis

In this paper, we present a hierarchical approach for constraint transformation. The important features of this are: a genetic algorithm (GA) based search engine that computes design parameter ranges, a hierarchically organized characterization mechanism based on the concept of directed intervals that assists the search engine and an analog performance estimator. Experiments were conducted comparing the hierarchical approach with a flat bottom-up one. The results obtained demonstrate the effectiveness of the former approach. Experimental results highlighting the impact of using the characterization information within the constraint transformation process are also presented.

A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis

In this paper, we present a genetic algorithm based constraint transformation method. A unique feature of this is performing system level parameter space exploration to generate component design parameter ranges. We discuss a theoretical formulation and also show the methods application in pruning the search space of an analog circuit synthesis tool. Finally experimental results showing the impact of parameter space exploration on circuit synthesis are presented.

Hierarchical constraint transformation based on genetic optimization for analog system synthesis

In a top-down analog system design methodology, the task of translating high-level performance specifications and constraints into component level parameters is termed as constraint transformation. In this paper, we presented a genetic optimization based approach to constraint transformation. The salient features of this are a search space profiling technique and a hierarchical two-level genetic optimization engine. Performance estimation for profiling and hierarchical optimization uses both the performance equations embedded in an analog performance estimation module as well as detailed SPICE simulation. We described the constraint transformation method, and each of its constituents. The effectiveness of the two-level hierarchical approach was established by comparing it against a flat non-hierarchical method. Application of the constraint transformation method in the synthesis of design examples was also presented in the paper.

Component characterization and constraint transformation based on directed intervals for analog synthesis

In this paper, we present a technique for characterizing CMOS analog circuits based on directed intervals. The technique consists of an analog performance estimator and a characterization table generator. This characterization information may be efficiently used by the constraint transformation step in an analog synthesis system. We present a genetic algorithm based constraint transformation method, that exploits problem structure by using the circuit characterization information. We discuss the design of the genetic operators that capture the characteristics of the constraint transformation problem. The constraint transformation method that uses the characterization information was compared against one using a conventional genetic algorithm and the experimental results obtained demonstrate the effectiveness of the proposed approach.

SRFCC: synthesis of RF CMOS circuits

In this paper, we present a methodology to synthesize CMOS RF devices from high-level circuit specifications into transistor netlists. The core of the methodology is an estimator of RF analog CMOS circuits, which evaluates the performance parameters of various circuit topologies. The estimation engine is based on a hierarchical analog performance estimator and a set of heuristics. The synthesis environment considers all performance parameters, and it relies on a genetic algorithm based heuristic method to search for a solution in a large design-space. The synthesis tool determines a solution set of design parameters such that the RF circuit satisfies the overall design constraints.

Automatic constraint transformation with integrated parameter space exploration in analog system synthesis

In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be confined to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher level on analog circuit synthesis are presented demonstrating the effectiveness of this technique.

Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with interconnects account for a significant part of the noise, delay and power associated with a signal. The estimation of interconnect lengths prior to placement helps in determining the performance of the circuit early in the design phase. Such estimations can provide circuit optimizations by re-ordering of logic blocks and thus reduce iterations between layout and synthesis. This paper presents a methodology to estimate the individual interconnect lengths in digital ICs, prior to layout. Estimations are from gate level netlist, and properties of a standard cell library. Various layouts have been studied to observe typical placement and routing patterns and these have been incorporated into our estimation methodology. Results obtained from the implementation of the methodology presented were compared with detailed routing wire lengths obtained after actual synthesis of the gate level netlist.