Afaq Ahmad

An efficient method to determine linear feedback connections in shift registers that generate maximal length pseudo-random up and down binary sequences

Based upon the mathematical characterization of linear feedback shift registers, an efficient algorithm for designing a maximal length pseudorandom binary sequence generator is postulated. The proposed algorithm is not only computationally cost effective in relation to existing algorithms, but also yields the knowledge of feedback connections corresponding to the reciprocal of each nth order primitive polynomial itself. This makes the algorithm a further, more effective tool for an LFSR based testing of digital circuits.

Are primitive polynomials always best in signature analysis

It is shown that in testing technique based on linear-feedback shift registers, the use of primitive polynomials in a signature-analysis register is not always better than using nonprimitive polynomials. The results show how some primitive polynomials may actually yield maximum aliasing errors. These results are based on the simulation of single stuck-at faults, but they also hold for certain multiple stuck-at faults. The best testing technique appears to be one that uses a binary counter in test-pattern generation with a primitive polynomial in signature analysis.<<ETX>>

Effectiveness of multiple compressions of multiple signatures

The feasibility of combining multiple signature and multiple compression techniques to achieve a further reduction in the frequency of aliasing is studied. A critical study of the impact of primitive polynomials on the effectiveness of the scheme has been made. The observations are demonstrated through simulation results.

Achievement of higher testability goals through the modification of shift registers in LFSR-based testing

The paper is devoted to the achievement of higher testability goals in the BIST environment through the modification of shift registers in LFSR-based testing. The aim is here to take the unified view of the effectiveness of various test-generation and response evaluation techniques with BIST capabilities to justify the design of unified built-in testing scheme. With this objective in mind, a comprehensive analysis of the principles involved has been undertaken to evolve an effective design approach for LFSR-based testing of combinational circuits. The proposed unified testing scheme is analysed through the testing of many ICs through a simulation study. Also, the design implementation of the scheme does not require extra hardware.

Critical role of polynomial seeds on the effectiveness of an LFSR-based testing technique

Abstract The impact of polynomial seeds on the effectiveness of a linear feedback shift register (LFSRrpar;-based testing technique is studied. The results of the study show that when the characteristic polynomials in the test-pattern generator, as well as in the signature analyser, are of same order and primitive, then any change in polynomial seed does not affect the probability of aliasing errors. The conclusion of this study is substantiated with extensive simulation data.

The use of irreducible characteristic polynomials in an LFSR based testing of digital circuits

The impact of irreducible characteristic polynomials with respect to polynomial seeds on the effectiveness of an LFSR (linear feedback shift register)-based testing technique is studied through a simulation experiment. The results reveal that when irreducible characteristic polynomials are used in after data compression, the behavior of aliasing errors, with respect to polynomial feeds, is unchanged. The same conclusion is arrived at by the simulation study of many more circuits. This result has an important bearing on an LFSR-based testing of digital circuits.<<ETX>>

Shift register modification for multipurpose use in combinational circuit testing

Abstract By modifying the shift registers of the commonly used built-in self-test (BIST) scheme, an effective multipurpose testing tool has been realized. The tool is capable of providing maximum enhancement in fault-cover, as well as significant improvement in error coverage.

On locking conditions in m-sequence generators for the use in digital watermarking

The maximal length pseudo random binary sequence is known as m-sequence. The m-sequence of domain {0, 1} can be represented in bipolar form of sequence in domain {−1, 1}. The m-sequences are used for watermarking because of their very good correlation properties, noise like characteristics and resistance to interference. This paper investigates a new locking condition in the operations of an m-sequence generator. Through this finding it is revealed that an LFSR structure may turn into locking state due to particular seed selection other than the all zeros or all ones.

An investigation into the application of linear feedback shift registers for steganography

Steganography is the art (as well as the science) of hiding information inside other innocuous data such that the very existence of the secret message is concealed from the eyes of the world. One of the techniques used in steganography to hide data behind images is called the least-significant bit (LSB) insertion wherein the LSB of each byte of the pixel of the images raster data is replaced with the single bit of the data to be hidden. This is based on the premise that the total number of bit-changes in the images raster data will be so small that the resulting stego-image will be indistinguishable to the human eye from the original image. In this paper, we propose to use random bit-sequences generated by linear feedback shift registers (LFSR) within the pixel-byte (instead of just the LSB) for the purpose of steganography. It is believed that such changes within any given pixel of the image will result in better hiding of the data and hence more secure data transmission.

Development of a Strong Stream Ciphering Technique Using Non-Linear Fuzzy Logic Selector

This paper introduces a new methodology of producing Pseudo- Random Binary Sequence (PRBS) of high complexity while with lesser burden of the processing requirements. The key idea behind the implementation of the proposed methodology is the use of a nonlinear fuzzy logic selector. A set of Linear Feedback Shift Registers (LFSRs) of nominal but varying lengths is used to reduce the processing as well as hardware burdens. In the proposed scheme, the LFSRs can be loaded with different configurations according to changed characteristic polynomials and polynomial seeds. This facilitation is being arranged such that they are to be selected by fuzzy logic selector switches. Further, the inputs to the fuzzy logic selector are based on user-defined parameters.