Agnes Verbist

IR bolometers made of polycrystalline silicon germanium

Abstract This paper reports the first fabrication of surface-micromachined microbolometers made of polycrystalline silicon-germanium alloy (poly Si 0.7 Ge 0.3 ). The electrical and mechanical properties of this material have been measured and the effects of the deposition conditions and annealing temperature on them have also been investigated. The complete process for the bolometer fabrication is presented and the possibility of reducing the process temperature to 650 °C is demonstrated. The thermal behaviour of the device is fully analysed and it is demonstrated that the use of poly Si 0.7 Ge 0.3 instead of polycrystalline Si (poly Si) decreases the thermal conductance of the device (values lower than 10 −6 W K −1 are obtained). Preliminary measurements give a value of 10 4 V W −1 for the IR responsivity.

Comparison between wet HF etching and vapor HF etching for sacrificial oxide removal

In this work the etching of different Si-oxide, Si-nitride and metal layers in HF:H2O 24.5:75.5, BHF:glycerol 2:1 and vapor HF is studied and compared. The vapor HF etching is done in a commercially available system for wafer cleaning, that was adapted according to custom specifications to enable stiction-free surface micro- machining. The etch rates as a function of etching method, time and temperature are determined. Moreover, the influence of internal and external parameters on the HF vapor etching process are analyzed before choosing the standard HF vapor etch technique used for comparing the etching behavior of the different films.

New low-stress PECVD poly-SiGe Layers for MEMS

Thick poly-SiGe layers, deposited by plasma-enhanced chemical vapor deposition (PECVD), are very promising structural layers for use in microaccelerometers, microgyroscopes or for thin-film encapsulation, especially for applications where the thermal budget is limited. In this work it is shown for the first time that these layers are an attractive alternative to low-pressure CVD (LPCVD) poly-Si or poly-SiGe because of their high growth rate (100-200 nm/min) and low deposition temperature (520/spl deg/C-590/spl deg/C). The combination of both of these features is impossible to achieve with either LPCVD SiGe (2-30 nm/min growth rate) or LPCVD poly-Si (annealing temperature higher than 900/spl deg/C to achieve structural layer having low tensile stress). Additional advantages are that no nucleation layer is needed (deposition directly on SiO/sub 2/ is possible) and that the as-deposited layers are polycrystalline. No stress or dopant activation anneal of the structural layer is needed since in situ phosphorus doping gives an as-deposited tensile stress down to 20 MPa, and a resistivity of 10 m/spl Omega/-cm to 30 m/spl Omega/-cm. With in situ boron doping, resistivities down to 0.6 m/spl Omega/-cm are possible. The use of these films as an encapsulation layer above an accelerometer is shown.

Planarization of deep trenches

The ability of various deposition processes and materials to fill and planarize topographical features (trenches deeper than 10 micrometers ) is investigated in this work. Three different deposition processes are considered: LPCVD (Ge), PECVD (Ge, Si3N4, SiO2) and spin coating (BCB, resist, polyimide). Comparing LPCVD and PECVD processes show that, for the same trench width, thick PECVD layers can close off trenches from the top, while thick LPCVD layers fill the trenches completely. The use of PECVD layers is thus advantageous for sealing applications, where a low bottom step coverage is desired. LPCVD layers on the other hand are very useful for planarization purposes where a low ratio between the deposited film thickness and the planarized trench width is desired. Also the deposition of polymers by spin coating yields excellent planarization results with a simpler process and lower thermal budget compared to LPCVD processes. All polymers investigated fill the trenches totally. If these planarization layers are used as sacrificial layers, they should be etched isotropically and selectively with respect to the structural layer. Ge can be etched in oxidizing solutions (H2O2/H2O) and the sacrificial etch of Ge is selective towards Si, SiO2 and many other layers. SiO2 can be removed by wet or vapor HF, and resist, polyimide and BCB can be removed by O2 or O2/SF6 plasma. Which layer should be used depends on the trench fill requirements, the thermal budget and the further processing needed.

Highly reliable CMOS-integrated 11MPixel SiGe-based micro-mirror arrays for high-end industrial applications

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.

Thermally insulated structures for IR bolometers, made of polycrystalline silicon germanium alloys

This paper reports the first realization of surface micromachined, suspended structures, made of poly crystalline silicon germanium alloys (poly Si/sub 0.7/Ge/sub 0.3/). The electrical and mechanical properties of this material are presented. The effect of the deposition conditions on the above properties is also investigated. The complete process for realizing the suspended structure is described and the possibility of reducing the process temperature down to 650/spl deg/C is demonstrated.

CMOS foundry-based micromachining

This paper reports on the first results of a study of the possibilities of the fabrication of micromechanical structures for microsystems applications in a regular MPC run of a standard CMOS process, followed by post-processing. Two post-processing modules, i.e., the frontside bulk etching module and the surface micromachining module are investigated. Examples of the former are suspended spiral coils for high-frequency applications and of the latter, metal bridge resonators.

Above-IC generic poly-SiGe thin film wafer level packaging and MEM device technology: Application to accelerometers

We present an attractive poly-SiGe thin film packaging and MEM (Micro Electro-Mechanical) platform technology for integrating various packaged MEM devices above standard CMOS. The packages, having cavities as large as 1mm2, make use of pillars designed to withstand subsequent molding during 1st level packaging. Covers on top of the release holes avoid deposition inside the cavity during sealing. Hermeticity is proven in vacuum, air and N2 atmosphere and at different temperatures. Packaged functional accelerometers sealed at a pressure around 1bar, have an equivalent performance in measuring accelerations of about 1g compared to a piezoelectric commercial reference device.

HF Etching of Si-Oxides and Si-Nitrides for Surface Micromachining

In this work the etching of Si-oxide, Si-nitride (LPCVD and PECVD) and Si-oxide/Si-nitride stacks in HF/H2O 263:73.7 and vapour HF is studied. Special attention is given to the residues, which were found to form during vapour HF etching of Si-nitride, PECVD Si-oxide and Si-oxide/Si-nitride stacks. These residues are not encountered during wet etching. Their origin and possible removal procedure are investigated.

Poly-SiGe-based CMUT array with high acoustical pressure

Capacitive micromachined ultrasound transducers (CMUT) have the potential to enable 3-D ultrasound imaging. This paper reports a novel manufacturable buildup of a CMUT device which is CMOS compatible. The approach allows high density integration and independent optimization of the CMUT device and the integrated electronics. The CMUT device makes use of polycrystalline silicon-germanium (poly-SiGe) as the structural material, in combination with silicon carbide (SiC) as the dielectric layer to allow high electrical field in the transduction gap. Breakdown voltage of above 500V is demonstrated. Transmit pressure normalized to the surface of the transducer is as high as 580kPa for DC and AC voltages of 340 and 75V, respectively. Initial characterization of pulse-echo measurement is also reported.