Simone Severi

Low-Loss Singlemode PECVD Silicon Nitride Photonic Wire Waveguides for 532–900 nm Wavelength Window Fabricated Within a CMOS Pilot Line

PECVD silicon nitride photonic wire waveguides have been fabricated in a CMOS pilot line. Both clad and unclad single mode wire waveguides were measured at λ = 532, 780, and 900 nm, respectively. The dependence of loss on wire width, wavelength, and cladding is discussed in detail. Cladded multimode and singlemode waveguides show a loss well below 1 dB/cm in the 532-900 nm wavelength range. For singlemode unclad waveguides, losses 1 dB/cm were achieved at λ = 900 nm, whereas losses were measured in the range of 1-3 dB/cm for λ = 780 and 532 nm, respectively.

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks.

Visible-to-near-infrared octave spanning supercontinuum generation in a silicon nitride waveguide

The generation of an octave spanning supercontinuum covering 488-978 nm (at -30  dB) is demonstrated for the first time on-chip. This result is achieved by dispersion engineering a 1-cm-long Si3N4 waveguide and pumping it with an 100-fs Ti:Sapphire laser emitting at 795 nm. This work offers a bright broadband source for biophotonic applications and frequency metrology.

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Aring, a leakage current of 1.5 A/cm2 at VG=1 V, a peak mobility of 190 cm2/Vmiddots, and a drive-current of 815 muA/mum at an off-state current of 0.1 muA/mum for VDD=1.2 V. Identical gate stacks processed with a 1000-degC spike anneal have a higher peak mobility at 275 cm2/Vmiddots, but a 5-Aring higher EOT and a reduced drive current at 610 muA/mum. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 degC) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V

A Reliable Metric for Mobility Extraction of Short-Channel MOSFETs

When comparing the extracted carrier mobility of long- and short-channel transistors, special consideration must be given to the metallurgical gate length (Lmet), neglecting the impact of source and drain junction profiles. Lmet can be identified with nanometer precision by using RF split-C-V measurements, and physical and electrical analysis can demonstrate the accuracy of the method. Another important parameter, the external transistor resistance (Rsd), can be identified with linear current measurements of short-channel devices. However, it is important to quantify the mobility dependence from the gate length in order to obtain an accurate result. A method to estimate the electrical field (Eeff) of short-channel devices is proposed. The extracted short-channel mobility shows a universal behavior identical to the classical long-channel one.

RF Split Capacitance–Voltage Measurements of Short-Channel and Leaky MOSFET Devices

In this letter, the feasibility of split-capacitance-voltage (C-V) measurements in the RF range is demonstrated. These RF/split-C-V measurements show excellent agreement with the values obtained by the low-frequency conventional technique but without presenting any noticeable degradation due to gate leakage

High performing 8 A EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown (SPER) junctions

We demonstrate high-performing w-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal budget process (570/spl deg/C anneal). The thinnest devices have an EOT of 8.3 A, a leakage current of 2.6 A/cm/sup 2/ at V/sub G/=1 V, and a drive-current of 815 /spl mu/A/um at an off-state current of 0.1 /spl mu/A//spl mu/m for VDD=1.2 V. We show that the performance improvement over identical gate-stacks processed with a 1000/spl deg/C spike anneal is related to a difference in V/sub T/.

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices

This paper reports on the successful integration of truly diffusion-less (less-than-650/spl deg/C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 /spl mu/A//spl mu/m for an off-state of 10 /spl mu/A//spl mu/m at Vdd= -1.2V and 1.4nm EOT SiON. We demonstrate that the gate de-activation problem associated with SPER is effectively solved by the use of the FUSI gate electrode. Super halo profiles are obtained with SPER, which opens up the halo design space for accurate SCE control. The junction leakage is greatly reduced by engineering the damage region away from the junction depletion region.

CMOS-Integrated Poly-SiGe Piezoresistive Pressure Sensor

An integrated poly-SiGe-based piezoresistive pressure sensor, which is directly fabricated above 0.13 m Cu-back-end CMOS technology, is presented. This represents not only the first integrated poly-SiGe pressure sensor directly fabricated above its readout circuit but also the first time that a poly-SiGe MEMS device is processed on top of Cu-back-end CMOS. Despite the low processing temperature (455°C) to allow for above-CMOS integration, the poly-SiGe piezoresistive sensor alone (250 250 m2 membrane) showed a sensitivity of around 2.5 mV/V/bar. The same sensor exhibited a sensitivity of 159.5 mV/V/bar after on-chip amplification. The CMOS circuit showed no significant deterioration after the MEMS processing, although a resistance increase for the Cu-filled metal-to-metal and the tungsten-filled CMOS-MEMS vias was observed.

Above-IC generic poly-SiGe thin film wafer level packaging and MEM device technology: Application to accelerometers

We present an attractive poly-SiGe thin film packaging and MEM (Micro Electro-Mechanical) platform technology for integrating various packaged MEM devices above standard CMOS. The packages, having cavities as large as 1mm2, make use of pillars designed to withstand subsequent molding during 1st level packaging. Covers on top of the release holes avoid deposition inside the cavity during sealing. Hermeticity is proven in vacuum, air and N2 atmosphere and at different temperatures. Packaged functional accelerometers sealed at a pressure around 1bar, have an equivalent performance in measuring accelerations of about 1g compared to a piezoelectric commercial reference device.