Bert Du Bois

Comparison between wet HF etching and vapor HF etching for sacrificial oxide removal

In this work the etching of different Si-oxide, Si-nitride and metal layers in HF:H2O 24.5:75.5, BHF:glycerol 2:1 and vapor HF is studied and compared. The vapor HF etching is done in a commercially available system for wafer cleaning, that was adapted according to custom specifications to enable stiction-free surface micro- machining. The etch rates as a function of etching method, time and temperature are determined. Moreover, the influence of internal and external parameters on the HF vapor etching process are analyzed before choosing the standard HF vapor etch technique used for comparing the etching behavior of the different films.

Poly-SiGe-Based MEMS Thin-Film Encapsulation

This paper presents an attractive poly-SiGe thin-film packaging and MEM (microelectromechanical) platform technology for the generic integration of various packaged MEM devices above standard CMOS. Hermetic packages with sizes up to 1 mm2 and different sealed-in pressures ( ~ 100 kPa and ~ 2 kPa) are demonstrated. The use of a porous cover on top of the release holes avoids deposition inside the cavity during sealing, but leads to a sealed-in pressure of approximately 100 kPa, i.e. atmospheric pressure. Vacuum ( ~ 2 kPa) sealing has been achieved by direct deposition of a sealing material on the SiGe capping layer. Packaged functional accelerometers sealed at around 100 kPa have an equivalent performance in measuring accelerations of about 1 g compared to a piezoelectric commercial reference device. Vacuum-sealed beam resonators survive a 1000 h 85°C/85%RH highly accelerated storage test and 1000 thermal cycles between -40°C and 150°C.

Simultaneous Optimization of the Material Properties, Uniformity and Deposition Rate of Polycrystalline CVD and PECVD Silicon-Germanium Layers for MEMS Applications

The deposition rate is significantly enhanced by utilizing a plasma-enhanced chemical vapor deposition (PECVD) method. This method produces however an amorphous SiGe deposition. To induce crystallization in the bulk PECVD layer it has to be deposited on top of a chemical vapor deposited (CVD) SiGe layer [4] which in itself is deposited on top of a thin PECVD seed layer (see Fig 1). The purpose of the PECVD seed layer is to minimize the incubation time. The CVD and PECVD depositions are performed sequentially in an Applied Materials Centura CxZ chamber.

SiGe MEMS technology: a platform technology enabling different demonstrators

In imecs 200mm fab a dedicated poly-SiGe above-IC MEMS (Micro Electro-Mechanical Systems) platform has been set up to integrate MEMS and its readout and driving electronics on one chip. In the Flemish project Gemini the possibilities of this platform have been further explored together with the project partners. Three different demonstrators were realized: mirrors for display applications, grating light valves (GLV) and accelerometers. Whereas the mirrors and GLVs are made with a similar to 300 nm thick SiGe structural layer plus optical coating, the SiGe structural layer thickness for the accelerometers is 4 mu m in order to improve the capacitive readout of in-plane devices. The processing and measurement results of these functional demonstrators are shown in this paper. These new demonstrators reconfirm the generic nature of the SiGe MEMS platform.

Improvement of PECVD Silicon–Germanium Crystallization for CMOS Compatible MEMS Applications

This paper investigates the influence of the electrode spacing, chamber pressure, total gas flow, and H 2 dilution on the crystallinity, resistivity, uniformity, and stress of polycrystalline silicon-germanium (poly-SiGe) films grown by plasma-enhanced chemical vapor deposition (PECVD). Boron-doped PECVD SiGe films of 1.6 μm thick are deposited on 400 nm chemical vapor deposition layers from SiH 4 , GeH 4 , and B 2 H 6 precursors. The microstructure is verified by transmission electron microscopy and by X-ray diffraction. It was discovered that for constant temperature and deposition rate, the PECVD SiGe microstructure changes from completely amorphous to polycrystalline by increasing the electrode spacing and pressure due to reduced ion bombardment. A process window of an electrode spacing and pressure for the PECVD poly-SiGe deposition is thus identified based on a sheet resistance mapping method. Increasing the total gas flow dramatically improves the within-wafer crystallinity variation and further reduces the resistivity. Increasing the H 2 flow during PECVD shifts the stress from -51 to 17 MPa and further reduces the crystallinity variation over the wafer. In addition, the effect of changing the SiH 4 to GeH 4 ratio and the in situ boron doping by adding B 2 H 6 is also investigated. The findings in this paper are expected to facilitate the use of poly-SiGe in the above complementary metal oxide semiconductor (CMOS) microelectromechanical system (MEMS) applications.

Apparent and steady-state etch rates in thin film etching and under-etching of microstructures: II. Characterization

The apparent and steady-state etch rates of PECVD SiO2, HDP SiO2 and PECVD Si3N4 are measured both in a single thin film and a stacked film configuration. This is done for a HF:H2O/1:1, a HF:IPA/1:1 and a BHF solution. It is shown that etch rates vary with the used etch time, confirming the influence of both an incubation and a rinsing period on the average etch rate when performing typical ex situ etch rate experiments. Hence, this second part of a set of two papers provides the experimental evidence for part I where a general etch rate model was proposed. Furthermore this work shows that the etch rate varies whether it is determined on a single layer, in a stacked configuration or while under-etching a structural layer. This confirms the need of a straightforward characterization method for under-etching measurements at the sacrificial release stage of MEMS fabrication processes. Therefore, a new characterization method, using a suspended beam array and a surface profilometer, is proposed to determine the amount of under-etch after sacrificial release of surface micromachined devices.

Stacked Boron Doped Poly-Crystalline Silicon-Germanium Layers: an Excellent MEMS Structural Material

In this work stacked boron doped poly-crystalline Silicon-Germanium (poly-SiGe) layers, which can be applied as structural MEMS layers, were studied. A standard 1 µm base layer, deposited at 480 oC chuck temperature, is stacked until the required thickness (e.g. 10 x for a 10 µm thick layer). This 1 µm base layer consists of a PECVD seed layer (+/− 75 nm), a CVD crystallization layer (+/− 135 nm) and a PECVD layer to achieve the required thickness with a high growth-rate. The top part of this PECVD layer can optionally be used for optimizing the stress gradient by a stress compensation layer. This approach resulted in 4 µm thick poly-SiGe MEMS structural layers with low tensile stress (50 MPa), low resistivity (2 mΩcm) and a low strain gradient ( −5 /µm).

SIGEM, low-temperature deposition of Poly-SiGe MEMs structures on standard CMOS circuits

Fabrication of surface-micromachined structures by a post-processing module above standard IC circuits is an efficient way to produce monolithic microsystems, allowing nearly independent optimization of the circuitry and the MEMS process. However, until now the high-temperature steps needed for deposition of poly-Si have limited its application. SiGeM explores the possibilities offered by the low-temperature (450°C) deposition and structuring of poly-SiGe layers, which is compatible with the temperature budget of fully-processed standard IC wafers. In the SiGeM project several low-temperature deposition methods (CVD, PECVD, LPCVD) were developed, and were evaluated with respect to growth rate and material quality. The interconnection technology to the underlying CMOS circuitry was also developed. The capabilities of this new integration technology will be demonstrated in a monolithic high-performance rate-of-turn sensor, currently considered the most demanding MEMs application in terms of material properties of the structural layer (thickness > 10mm, stress gradient < 0.3MPa/mm) and signal processing circuitry (capacitance resolution in the aF range, SNR > 110 dB). System partitioning will combine analog and DSP circuit techniques to maximize resolution and stability. Parasitic electrical coupling within different parts of the system has been analyzed, and countermeasures to reduce it have been incorporated in the design. The feasibility of the approach has already been proved by preliminary characterization of working prototypes containing released microstructures deposited on top of preamplifier circuits built on a 0.35mm, 5-metal, 2-poly, standard CMOS process from Philips Semiconductors. Resonance frequencies are in good agreement with predictions, and quality factors above 8000 have been obtained at pressures of 0.8 mTorr. Measured SNR confirms the capability to achieve a resolution of 0.015°/s over a bandwidth of 50 Hz.