Agostino Macerola
Micron Technology
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Publication
Featured researches published by Agostino Macerola.
international solid-state circuits conference | 2010
Giulio Marotta; Agostino Macerola; Andrea D'Alessandro; A. Torsi; C. Cerafogli; C. Lattaro; C. Musilli; D. Rivers; E. Sirizotti; F. Paolini; Giuliano Gennaro Imondi; Giovanni Naso; Giovanni Santin; L. Botticchio; L. De Santis; Luigi Pilolli; Maria Luisa Gallese; Michele Incarnati; Marco-Domenico Tiburzi; Pasquale Conenna; S. Perugini; Violante Moschiano; W. Di Francesco; M. Goldman; Chris Haid; D. Di Cicco; D. Orlandi; F. Rori; Massimo Rossini; Tommaso Vali
In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm2.
international solid-state circuits conference | 2016
Tomoharu Tanaka; Mark A. Helm; Tommaso Vali; Ramin Ghodsi; Koichi Kawai; Jae-Kwan Park; Shigekazu Yamada; Feng Pan; Yuichi Einaga; Ali Ghalam; Toru Tanzawa; Jason Guo; Takaaki Ichikawa; Erwin Yu; Satoru Tamada; Tetsuji Manabe; Jiro Kishimoto; Yoko Oikawa; Yasuhiro Takashima; Hidehiko Kuge; Midori Morooka; Ali Mohammadzadeh; Jong Kang; Jeff Tsai; Emanuele Sirizotti; Eric N. Lee; Luyen Vu; Yuxing Liu; Hoon Choi; Kwonsu Cheon
A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.
international solid-state circuits conference | 2013
Giovanni Naso; L. Botticchio; M. Castelli; C. Cerafogli; M. Cichocki; P. Conenna; Andrea D'Alessandro; Luca De Santis; Domenico Di Cicco; W. D. Francesco; M. L. Gallese; Girolamo Gallo; Michele Incarnati; C. Lattaro; Agostino Macerola; Giulio Marotta; Violante Moschiano; D. Orlandi; F. Paolini; S. Perugini; Luigi Pilolli; P. Pistilli; G. Rizzo; F. Rori; Massimo Rossini; Giovanni Santin; E. Sirizotti; A. Smaniotto; U. Siciliani; Marco-Domenico Tiburzi
The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.
Archive | 2009
Agostino Macerola; Giulio-Giuseppe Marotta; Marco-Domenico Tiburzi
Archive | 2012
Agostino Macerola; Giulio-Giuseppe Marotta
Archive | 2005
Agostino Macerola
Archive | 2003
Giulio Marotta; Agostino Macerola
Archive | 2013
Chiara Cerafogli; Agostino Macerola
Archive | 2012
Agostino Macerola
Archive | 2012
Agostino Macerola
