Ah-Reum Kim

Single-ended D flip-flop with implicit scan mux for high performance mobile AP

A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradation on a data path. The proposed flip-flop enables to achieve the high-speed operation having the comparable hold time characteristics to a conventional master-slave flip-flop without any writeability issue at low voltage. The simulated and the measured results were made using a 14nm FinFET process. The data-to-output latency of the proposed flip-flop decreased by 51% while the power delay product improved by 41% as compared with the master-slave flip-flop. A test chip was fabricated in SS, TT, FF, SF and FS process corners and tested at −25C and 100C with a 50mV voltage step from 0.45V to 1.00V. It indicates both the master-slave and the proposed flip-flops can work down to 0.50V whereas conventional pulse-based flip-flops have writeability problems at 0.60V. Two product-level CPU designs were also fabricated for performance comparison, leading to 8.5% speed improvement by applying the proposed high-speed flip-flop.

22.1: Low Power Driving Scheme for High Frame Rate LCD TVs

Recently, there have been lots of demands for green products. One of solutions is to reduce the power consumption. Whereas the most approaches in liquid crystal displays (LCDs) are focused on reduction of the backlight power consumption with local dimming technologies, this paper proposes the new low power driving scheme for LCD TV panels operated at high frame rates of 120Hz and 240Hz. Dynamic and static power consumptions have been lowered by means of the frame rate reduction for still input image and fallback and the charge sharing method applied at the vertical blank period. As the maximum, the total power can be reduced to around 50% and 75% for 120Hz and 240Hz.

64.3: Design of Partially Cascaded Clock‐Embedded Serial Link Intra‐Panel Interface for a Flat Panel Display System

A partially cascaded clock-embedded serial link has been designed as an intra-panel interface between a timing controller (TCON) and column driver ICs (DICs) in an LCD panel. The proposed link achieves a 60Hz full-HD display of 10-bit color depth on only four interface pairs. Compared to a conventional point-to-point interface, further reduction of the number of interface lines has been achieved by means of a bandwidth efficient cascaded scheme.