Chung-Hee Kim

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor

The demands for high-performance smart mobile devices are growing exponentially every year. Like the PC market, 64b CPUs are needed to meet this demand. Furthermore, mobile GPU performance is becoming increasingly important as mobile game graphics requirements are pushing the limits of GPU capabilities. For an enhanced mobile game user experience, a multi-core GPU is required. CPU/GPU power efficiency for longer battery life has been a major interest to consumers for many years. In order to support higher performance and power efficiency, two 64b quad-core CPUs with different microarchitectures and a hexa-core GPU are implemented using Samsungs 20nm gate-last high-k/metal-gate (HKMG) process.

Scan-controlled pulse flip-flops for mobile application processors

Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and scan enable signals are presented. The proposed scheme enables the reduction of data-to-output delay by elimination of the MUX-scan logic from the setup time path of flip-flop, at the cost of a small power overhead. The comparison results using the 45 nm CMOS process indicate that the worst-case DQ delay of the proposed flip-flop is reduced by up to 59% while the energy-delay product is improved by up to 80% compared to the conventional master-slave flip-flop. The silicon results show that the new flip-flops function properly down to 0.62 V.

Single-ended D flip-flop with implicit scan mux for high performance mobile AP

A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradation on a data path. The proposed flip-flop enables to achieve the high-speed operation having the comparable hold time characteristics to a conventional master-slave flip-flop without any writeability issue at low voltage. The simulated and the measured results were made using a 14nm FinFET process. The data-to-output latency of the proposed flip-flop decreased by 51% while the power delay product improved by 41% as compared with the master-slave flip-flop. A test chip was fabricated in SS, TT, FF, SF and FS process corners and tested at −25C and 100C with a 50mV voltage step from 0.45V to 1.00V. It indicates both the master-slave and the proposed flip-flops can work down to 0.50V whereas conventional pulse-based flip-flops have writeability problems at 0.60V. Two product-level CPU designs were also fabricated for performance comparison, leading to 8.5% speed improvement by applying the proposed high-speed flip-flop.

Power and Skew Aware Point Diffusion Clock Network

This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm 2 CortexA-8 core with 65 nm Samsung process.