Ahmad Yasin

A Top-Down method for performance analysis and counters architecture

Optimizing an applications performance for a given microarchitecture has become painfully difficult. Increasing microarchitecture complexity, workload diversity, and the unmanageable volume of data produced by performance tools increase the optimization challenges. At the same time resource and time constraints get tougher with recently emerged segments. This further calls for accurate and prompt analysis methods. The insights from this method guide a proposal for a novel performance counters architecture that can determine the true bottlenecks of a general out-of-order processor. Unlike other approaches, our analysis method is low-cost and already featured in in-production systems - it requires just eight simple new performance events to be added to a traditional PMU. It is comprehensive - no restriction to predefined set of performance issues. It accounts for granular bottlenecks in super-scalar cores, missed by earlier approaches.

Compiler-Directed Power Management for Superscalars

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building a power delivery network for the worst-case power consumption is not energy efficient and often is impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this article, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems

A detailed analysis of power consumption at low system levels becomes important as a means for reducing the overall power consumption of a system and its thermal hot spots. This work presents a new power estimation method that allows understanding the power breakdown of an application when running on modern processor architecture such as the newly released Intel Skylake processor. This work also provides a detailed power and performance characterization report for the SPEC CPU2006 benchmarks, analysis of the data using side-by-side power and performance breakdowns, as well as few interesting case studies.

A methodology for OLTP micro-architectural analysis

Micro-architectural analysis is critical to investigate the interaction between workloads and processors. While todays aggressive out-of-order processors provide a rich set of performance events for deep execution cycle analysis, OLTP characterization studies usually use a cache-miss-based method (CMBM). In this work, we investigate the validity and the functionality of CMBM by comparing it with Intels state-of-the-art Top-down Micro-architecture Analysis Method (TMAM) for OLTP workloads. We show that, while CMBM and TMAM provide a similar high-level micro-architectural behavior, it is inadequate for a fine-grained micro-architectural analysis. We further show that TMAM underestimates memory stalls. We optimize TMAMs execution cycle breakdown, and improve its estimation of memory stalls up to 50%.

Inside 6th gen Intel ® Core™: New microarchitecture code named skylake

•Skylake delivers record levels of performance and battery life in many personal computing use cases and form factors •Intel® Speed Shift Technology provides higher performance, responsiveness and efficiency at power constrained form factors •Skylake Processor Graphics delivers scalable performance, >1TFLOPS compute, enhanced low power media engines, flexible power management, and end-to-end 4K experience •Skylake family of products allows developers to: •Choose from wide range of platform capabilities •Innovate with products for wide range of thermal envelopes and I/O solutions •Optimize the system performance using the advanced PMU capabilities •Skylake introduces Intel® SGX: a revolutionary game changer to trusted application security in the main stream SW environment