Efraim Rotem

Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge

Modern microprocessors are evolving into system-on-a-chip designs with high integration levels, catering to ever-shrinking form factors. Portability without compromising performance is a driving market need. An architectural approach thats adaptive to and cognizant of workload behavior and platform physical constraints is indispensable to meeting these performance and efficiency goals. This article describes power-management innovations introduced on Intels Sandy Bridge microprocessor.

Multiple clock and voltage domains for chip multi processors

Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. CMP is becoming important by delivering more compute performance within the power constraints. Dynamic Voltage and Frequency Scaling (DVFS) has been studied in past work as a mean to increase save power and improving the overall processors performance while meeting the total power and/or thermal constraints. For such systems, power delivery limitations are becoming a significant practical design consideration, unfortunately this aspect of the design was almost ignored by many research works. This paper explores the various possible topologies to build a high end multi-core CPU and the available policies that maximize performance within the set of physical limitations. It evaluates single and multiple voltage and frequency domains and introduces a new clustered topology, grouping several cores together. A hybrid model, using measurements of a real CPU, cycle accurate simulator and an analytical model is introduced. The results presented indicate that considering power delivery limitations diverts the conclusions when such limitations are ignored. This paper shows that a single power domain topology performs up to 30% better than multiple power domains on light-threaded workload. In the fully threaded application the results divert. Clustered topology performs well for any number of threads.

Power and thermal constraints of modern system-on-a-chip computer

Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. For high end processors, junction temperature has been considered the toughest physical constraint that needs to be tightly managed. Recent trends in form-factors and the increased focus on thin and light systems such as Ultra Book, tablet computers and smartphones, shift the challenge away from junction temperature. Ergonomic thermal considerations and power delivery are becoming the limiters for delivering high computational performance density and need to be managed and controlled. In this paper we describe the major physical constraints, design considerations and modern power and thermal management techniques and demonstrate them on an Intel Core(tm) i7 system.

Compiler-Directed Power Management for Superscalars

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building a power delivery network for the worst-case power consumption is not energy efficient and often is impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this article, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

H-EARtH: Heterogeneous Multicore Platform Energy Management

By scheduling each workload according to its most advantageous core and managing voltage and frequency, the heterogeneous energy-aware race to halt (H-EARtH) algorithm optimizes CPU platform energy.

Energy management of highly dynamic server workloads in an heterogeneous data center

We propose a hybrid management model to address heterogeneous data center energy efficiency with highly dynamic workload. A central dispatch and control algorithm with distributed system energy management was implemented and validated on real processor and system. We demonstrate up to 20% energy savings (11% average) without compromising quality of service. Additional 5% average energy savings was achieved by exploiting system heterogeneity.

Inside 6th gen Intel ® Core™: New microarchitecture code named skylake

•Skylake delivers record levels of performance and battery life in many personal computing use cases and form factors •Intel® Speed Shift Technology provides higher performance, responsiveness and efficiency at power constrained form factors •Skylake Processor Graphics delivers scalable performance, >1TFLOPS compute, enhanced low power media engines, flexible power management, and end-to-end 4K experience •Skylake family of products allows developers to: •Choose from wide range of platform capabilities •Innovate with products for wide range of thermal envelopes and I/O solutions •Optimize the system performance using the advanced PMU capabilities •Skylake introduces Intel® SGX: a revolutionary game changer to trusted application security in the main stream SW environment