Ahmad Yazdi

Design and analysis of an ultrawide-band distributed CMOS mixer

This paper presents the design and analysis of a novel distributed CMOS mixer for ultrawide-band (UWB) receivers. To achieve the UWB RF frequency range required for the UWB communications, the proposed mixer incorporates artificial inductance-capacitance (LC) delay lines in radio frequency (RF), local oscillator (LO), and intermediate frequency signal paths, and single-balanced mixer cells that are distributed along these LC circuits. Closed-form analytical model for the conversion gain of the mixer is presented. Furthermore, a comprehensive noise analysis of the proposed distributed mixer is carried out, which includes calculation of the mixer noise figure (NF) and derivation of the optimum number of stages, n, minimizing the NF. The designed mixer is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz. A two-stage distributed mixer has been fabricated in a 0.18-/spl mu/m CMOS process. Experiments show a conversion gain of more than 2.5 dB for the entire range of the frequencies. The dc power consumption is 10.4 mW.

A 1.8V three-stage 25GHz 3dB-BW differential non-uniform downsized distributed amplifier

A three-stage nonuniform downsized distributed amplifier is realized in a 0.18/spl mu/m SiGe process, using CMOS transistors only. The amplifier achieves the differential forward gain of 7.8dB over a 25GHz bandwidth and an IIP3 of +4.7dBm. The 1.025/spl times/1.29mm/sup 2/ chip dissipates 54mW from a 1.8V supply.

A 40 GHz Differential Push-Push VCO in 0.18

A 40 GHz differential CMOS push-push VCO is proposed for high-frequency applications. It is shown analytically that the phase noise of the VCO output at the full-rate frequency is close to 6 dB higher than that of the half-rate frequency. The result of the phase noise analysis is verified by simulations and measurements. A phase noise of - 101 dBc/Hz was achieved at 1 MHz offset frequency. The proposed push-push VCO design enables higher VCO frequency operation with differential output, which is suitable for millimeter wave frequency synthesizers.

\mu{\rm m}

This paper presents the design and fabrication of an LNA and a mixer for a multiband UWB wireless receiver using distributed circuit topologies. First, the design of a 3-stage CMOS distributed LNA circuit consisting of three cascode cells is introduced. Next, the design of a 2-stage CMOS distributed mixer consisting of two single-balanced cells is presented. The LNA and mixer circuits are separately designed and fabricated in a 0.18 /spl mu/m CMOS process. The LNA circuit achieves a 2.9 dB NF over the entire 7.5 GHz BW. It exhibits a forward gain of 8 dB, and an IIP3 of -3.4 dBm. The mixer circuit is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz.

CMOS for Serial Communication

In this paper a non-uniform distributed amplifier is presented. Decreasingly scaling of the device and inductor sizes of a distributed amplifier will result in a better voltage and power gain-bandwidth product. A comprehensive analytical study has been done and simulations confirm the superiority of the proposed nonuniform distributed amplifier compared to its conventional counterpart in terms of a better gain-bandwidth product and more flat frequency response.

Design of CMOS distributed circuits for multiband UWB wireless receivers [LNA and mixer]

Serial data communication systems operating at throughputs of 40Gb/s have been developed in recent years to increase transmission capacity. A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe, GaAs and InP at speeds of 40Gb/s or higher [1–3]. CMOS implementations of half-rate MUX circuits have been also reported [4–5]. A full-rate architecture would be desirable in order to reduce the deterministic jitter. This paper describes high-speed design techniques used for retiming of 40Gb/s data signals and generation of 40GHz clock signals.

A novel non-uniform distributed amplifier

In this paper, the design and analysis of a novel non-uniform fully differential distributed amplifier is presented. The gain-bandwidth product of the proposed amplifier designed in a 0.18 /spl mu/m standard CMOS process reaches a record level of 34.76 GHz. Proved by both the analytical models and the HSPICE simulations, down-sizing the device and inductor sizes of each stage with respect to the preceding stage in a distributed amplifier results in a better gain-bandwidth product. A comprehensive analytical study is carried out to predict the behavior of the amplifier. HSPICE simulations verify the superior performance of the proposed non-uniform distributed amplifier compared to its conventional counterpart in terms of a better gain-bandwidth product and a flat frequency response.

A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS

This paper demonstrates high-speed design techniques that enable realization of a full-rate broadband serializer operating at 40 Gb/s using a 0.18-μm CMOS process. Bandwidth enhancement techniques, including shunt-peaking and multipole bandwidth enhancement, have been incorporated in the different high-speed blocks in the serializer. A dynamic retiming circuit capable of clocked 40-GHz operation is presented, which reduces the periodic jitter at the serial output. A low-power distributed buffer with unequal characteristic impedances in the gate line and drain line is designed as a 40-Gb/s output buffer. A method for generating a differential 40-GHz clock using two coupled 20-GHz oscillators with a “push-push” topology is also presented. An injection-locked divider based on a four-stage ring oscillator with four injection points has been designed for generating a 10-GHz clock signal.