A. Shameli

A Two-Point Modulation Technique for CMOS Power Amplifier in Polar Transmitter Architecture

A two-point modulation technique is presented that improves the performance of nonlinear power amplifiers (PAs) in polar transmitters. In this scheme, the output amplitude modulation is performed by controlling the current of the PA. The current control technique enables the PA to provide wideband amplitude modulation, as well as high power control dynamic range. In addition, the supply voltage of the PA is adjusted based on the output power level. The voltage supply adjustment substantially improves the effective power efficiency of the PA. The voltage supply control is performed using a second-order sigma-delta dc-dc converter, which presents an efficiency of over 95% in its operational range. The PA operates at 900 MHz with maximum output power of 27.8 dBm and power efficiency of 34% at maximum output power. The proposed PA achieves 62-dB power control dynamic range with amplitude modulation bandwidth of over 17.1 MHz. The circuits are fabricated in a CMOS 0.18 mum process with a 3.3-V power supply.

Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study

This paper studies the use of moderately inverted MOS transistors in ultra-low power (ULP) RFIC design. We introduce a new figure of merit for a MOS transistor, i.e., the gmfT-to-current ratio, (gmfT/ID) which accounts for both the unity-gain frequency and current consumption during the optimization process of the transistors performance. Using this figure of merit while taking into account the velocity saturation of short-channel MOS devices, it is shown both experimentally and analytically that the gmfT/ID reaches its maximum value in moderate inversion region. Moreover, we analytically investigate the noise behavior of the MOS transistor during the transition from weak inversion to strong inversion region. The measurement results have been obtained for an NMOS transistor fabricated in Jazz Semiconductors CMOS process

RF Identification (RFID) Reader Front Ends With Active Blocker Rejection

This paper presents a novel active blocker rejecting RF (ABR-RF) front end for RF identification (RFID) applications. The proposed ABR-RF injects the blocker replica within the low-noise amplifier of the RFID receiver chain, through a feed-forward path to actively create an arbitrary narrowband notch filtering for the in-band blockers, while not affecting the gain of the desired signal. The in-band blocker is from the leakage of the RFID self-transmitter because RFID systems use backscattering communication. The notch frequency of the ABR-RF is always locked to the RFID transmitter frequency without any passive element tuning. Fabricated in a 0.18- mum CMOS technology, the prototype improves the ABR-RFs 1-dB compression point by greater than 18 dB, and achieves a 50-dB signal-to-blocker ratio improvement. The receiver path draws 40 mA from a 1.8-V supply voltage. The blocker filtering path adds maximum of 16 mA to reject a maximum in-band blocker of 20 dBm. The die area is 1.8 times 1.2 mm2.

An Integrated RFID Reader

A UHF RFID reader that handles RFID tag information as weak as -80dBm along with large inband blockers as large as 20dBm is presented. Fabricated in a 0.18mum CMOS process, the reader selectively attenuates large inband blockers, 40 to 250kHz away from the tag information, by better than 30dB using the limiting concept, while amplifying the tag information by 18dB.

A Novel Ultra-Low Power (ULP) Low Noise Amplifier using Differential Inductor Feedback

A novel ultra-low power (ULP) low noise amplifier (LNA) is proposed for low-power radio-frequency (RF) wireless radios. Using the differential inductor feedback structure along with the neutralizing capacitor, this configuration doubles the effective gm of the input transistor, while canceling out the feed forward and LO leakage through the gate-drain capacitor. In this design, the input device is biased to operate in moderate inversion region to achieve microwatt power dissipation. Experimental results indicate a power dissipation of 100muW, a noise-figure (NF) of 3.9dB, and a forward gain of 16.8dB. The LNA also exhibits an 1IP3 of -11.2dBm and the input referred -1dB compression point of -21dBm. The circuit was fabricated in Jazz Semiconductors CMOS 0.18mum process and was powered up using a supply voltage of 1V. For comparison purpose, a ULP common-gate LNA was also designed and fabricated using the same process. Experimental results show that the proposed LNA exhibits higher gain, lower NF, and better linearity

Design of CMOS distributed circuits for multiband UWB wireless receivers [LNA and mixer]

This paper presents the design and fabrication of an LNA and a mixer for a multiband UWB wireless receiver using distributed circuit topologies. First, the design of a 3-stage CMOS distributed LNA circuit consisting of three cascode cells is introduced. Next, the design of a 2-stage CMOS distributed mixer consisting of two single-balanced cells is presented. The LNA and mixer circuits are separately designed and fabricated in a 0.18 /spl mu/m CMOS process. The LNA circuit achieves a 2.9 dB NF over the entire 7.5 GHz BW. It exhibits a forward gain of 8 dB, and an IIP3 of -3.4 dBm. The mixer circuit is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz.

An RFID System with Fully Integrated Transponder

This paper presents an RFID system with fully integrated transponder. The transmit path of the reader as well as key blocks of the tag is designed and fabricated in standard CMOS 0.18 mum process. The system operates at 900 MHz with the coverage range of more than 0.4 cm. The tags antenna is integrated on chip without using any special process. The reader employs a coil switching technique to increase its coverage area. The PA in the transmit path of the reader is designed using digital to RF configuration. By employing a proper output network, the PA can deliver a current of 225 mA (RMS) to the readers coil.

A Novel DAC Based Switching Power Amplifier for Polar Transmitter

A novel switching power amplifier based on the concept of digital to analog converter (DAC) is presented for polar transmitter architecture. The novel idea in this amplifier is to generate a current proportional to the amplitude modulation signal and the power control bits. The current is then up-converted to the frequency of interest using switching transistors. In this paper, we demonstrate that the performance of the proposed circuit is superior compare to the existing power amplifiers designed for polar transmitter. The measurement results show maximum output power of 27.8dBm with power efficiency of 34%. Moreover, the amplifier exhibits amplitude modulation bandwidth of 4.2MHz and 62dB power control dynamic range. The circuit is fabricated in CMOS 0.18mum process with 3.3V power supply