Michael M. Green

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.

High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz

The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-/spl mu/m CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.

How to identify unstable DC operating points

The stability of operating points that satisfy the circuits DC operations but are nonetheless unobservable operating points is examined in a rigorous way. Two classes of DC operating points, unstable and potentially stable, are defined, and simple criteria, based only on the circuits DC equations, that can classify a given operating points stability are given. It is also shown that it suffices to model stray capacitance and inductance in only certain specific locations, for any given physical circuit, to correctly assess the stability of its operating point in the presence of a profusion of parasitic reactances. >

Dynamics of high-frequency CMOS dividers

Frequency dividers are an essential part of broadband communications ICs. They are often the most difficult part of a circuit designed to operate at very high frequencies, especially in CMOS. In order to optimize the circuit for high frequency performance, it is necessary to understand the dynamics of the dividers. This paper presents an analysis of the dynamics of high frequency CMOS dividers and sets some guidelines for circuit design.

A 10 Gb/s BiCMOS adaptive cable equalizer

A 10 Gb/s adaptive equalizer IC using SiGe BiCMOS technology is described. The circuit consists of the combination of an analog equalizer and an adaptive feedback loop for minimizing the inter-symbol interference (ISI) for a variety of cable characteristics. The adaptive loop functions using a novel slope-detection circuit which has a characteristic that correlates closely with the amount of ISI. The chip occupies an area of 0.87 mm/spl times/0.81 mm and consumes a power of 350 mW with 3.3 V power supply. This adaptive equalizer is able to compensate for a cable loss up to 22dB at 5 GHz while maintaining a low bit-error rate.

An 80 mW 40 Gb/s 7-Tap T /2-Spaced Feed-Forward Equalizer in 65 nm CMOS

A 7-tap 40 Gb/s FFE using a 65 nm standard CMOS process is described. A number of broadbanding and calibration techniques are used, which allow high-speed operation while consuming 80 mW from a 1 V supply. ESD protection is added to 40 Gb/s IOs and an inexpensive plastic package is used to make the chip closer to a commercial product. The measured tap delay frequency response variation is less than 1 dB up to 20 GHz and tap-to-tap delay variation is less than 0.3 ps. More than 50% vertical and 70% horizontal eye opening from a closed input eye are observed. The use of a CMOS process enables further integration of this core into a DFE equalizer or a CDR/Demux based receiver.

A fully integrated SONET OC-48 transceiver in standard CMOS

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-/spl mu/m CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.

(Almost) half of any circuit's operating points are unstable

This paper presents new results concerning the stability of operating points of dc circuits. The authors define two classes of unstable operating points and develop criteria for identifying the class to which a given operating point belongs. They also show, by employing results from degree theory, that if a circuit possesses n structurally stable operating points (n has been shown previously to be odd), then /spl frac12/(n/spl minus/1) of these operating points must be unstable and hence physically unobservable. A special case of this result proves that any bistable circuit must possess at least three operating points. >

A BiCMOS 10Gb/s adaptive cable equalizer

An adaptive cable equalizer for 10 Gb/s broadband data, using a SiGe BiCMOS process, is presented. The circuit consists of a feed-forward equalizer that compensates for a copper cable length between 4 and 15 feet. Adaptation is performed by sensing the transition time of the equalizer output using a circuit based on the source-coupled node of a differential pair.

OC-192 transmitter in standard 0.18/spl mu/m CMOS

A fully integrated SONET OC-192 transmitter IC using a standard CMOS process consists of an input data register, FIFO, CMU, and 16:1 multiplexer to give a 10Gb/s serial output. A higher FEC rate, 10.7Gb/s, is supported. This chip, using a 0.18/spl mu/m process, exceeds SONET requirements, dissipating 450mW.