Ahmadreza Rofougaran

A 900 MHz CMOS LC-oscillator with quadrature outputs

The local oscillator (LO) in a wireless transceiver satisfies many exacting requirements. A variable frequency enables a phase-locked loop (PLL) to servo the LO to a stable lower frequency reference, or to correct frequency errors from measurements on the received signal. A low phase noise ensures little interference with nearby channels. A large LO voltage-swing means that it can drive a mixer with greater linearity. Finally, in single-sideband applications, the LO must supply precise quadrature phases. Low phase noise mandates use of a high-Q resonator to tune the LO, although most RF resonators are usually not integrable on ICs. Quadrature outputs are usually derived from RC phase-shift of a single-phase LO output, but this is susceptible to component inaccuracy and loss in LO amplitude. The authors present a 900 MHz oscillator circuit implemented in 1 /spl mu/m CMOS that affords modestly low-phase noise, has variable frequency with large output swing, and provides quadrature-phase outputs from two identical coupled oscillators, connected in such a way that they exert a mutual squelch when their relative phase is not in quadrature. The coupled oscillators synchronize to exactly the same frequency, in spite of mismatches in their resonant circuits.

A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver

An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 /spl mu/m CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers.

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-/spl mu/m CMOS. I. Architecture and transmitter design

A single-chip transceiver for frequency-hopped code division multiple access (CDMA) in the 900 MHz industrial, scientific and medical (ISM) band is implemented in 1-/spl mu/m CMOS. It combines a digital frequency synthesizer, a double quadrature upconverter, an integrated oscillator, and a power amplifier with variable output. Data modulates a carrier hopping at 20 kHz with quaternary frequency-shift keying (4-FSK). At an output power level of +3 dBm, the harmonics and spurious tones lie at -52 dBc or below. When active, the transmitter drains 100 mA from 3 V.

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-/spl mu/m CMOS. II. Receiver design

For pt. I see ibid., vol. 33, no. 4, April 1998. A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the data decisions. The received signal is dehopped when it is down-converted. The cascade noise figure is 8.6 dB, and the cascade IIP3 is -8.3 dBm. In active mode, the receiver takes 120 mA from 3 V.

A CMOS channel-select filter for a direct-conversion wireless receiver

This paper describes the design and performance of an SC channel select filter for a frequency-hopped spread-spectrum direct-conversion receiver operating in the 902-926 MHz ISM band. Data modulates a hopped carrier by one of two (or four) prescribed frequency offsets, such that the modulated spectrum is always contained within +200 kHz of the carrier. Following preselection of the 26 MHz-wide ISM band at RF, an agile local oscillator synchronized to the hopping pattern of the received signal downconverts the band to bring the sought channel to DC. The channel-select filter passband extends 220 kHz around DC, and the adjacent channel 320 kHz away from the carrier defines the filters stopband edge. System simulations suggest that if all ISM-band users in a cell abide by power control, then to detect the desired channel with a sufficiently high signal-to-interference ratio, the filter must attenuate adjacent channels by at least 45 dB.

The future of CMOS wireless transceivers

Building blocks alone do not account for the current interest in CMOS for RF applications. The more compelling reason is the opportunities CMOS affords for large-scale integration. Modern wireless transceivers will increasingly blend digital blocks into conventional analog front-ends for frequency synthesis, adaptivity, multi-mode operation, and sophisticated detection. This raises questions such as how well digital CMOS circuits can co-exist on the same substrate as the radio front-end, or whether there is sufficient on-chip isolation in a low-cost package to guarantee stable operation of a receiver with more than 100 dB of baseband gain, or how the power amplifier modulates the on-chip local oscillator. The future of CMOS transceivers may well depend on satisfactory answers to these questions. This paper presents design techniques to mitigate these problems in a single-chip 900 MHz spread-spectrum transceiver implemented in 1 /spl mu/m CMOS, and measurements of the transceiver to validate their effectiveness.

A CMOS limiting amplifier and signal-strength indicator

Although all commercially available monolithic log amps today are bipolar ICs, CMOS is equally well-suited to implement the successive-detection architecture. We report here on the design and performance of such a logarithmic amplifier, which is part of a monolithic all-CMOS spread-spectrum 900 MHz wireless transceiver. In the intended use, a received 160 kb/s binary-FSK signal is amplified at RF, directly downconverted to DC, and applied to the logarithmic amplifier after channel-select filtering. The amplifier provides two useful outputs. First, the limited output from the cascade of clipping amplifiers contains the data encoded as signal phase in the zero-crossings. Second, the circuit produces a logarithmic signal-strength measurement to an accuracy of 1 dB over a 80 dB dynamic range.

An all-CMOS architecture for a low-power frequency-hopped 900 MHz spread spectrum transceiver

An all-CMOS single chip architecture of a frequency-hopped spread spectrum (FH/SS) transceiver is presented. The transceiver implements complete modem functions spanning a tuned RF front-end to a digital binary frequency-shift keying (FSK) modulator/demodulator, all operating from a 3-V supply. This FH/SS transceiver is intended for use in a wide variety of indoor/outdoor portable wireless applications in the 902-928 MHz ISM band [1]. System features such as dual antenna/branch diversity, fast frequency hopping, and adaptive power control are incorporated into the transceiver architecture to achieve robust wireless digital data transmission over multipath fading channels. This paper describes the architectural features of the transceiver and surveys several of the key building blocks which have been completed to date.<<ETX>>

A low-power CMOS digitally synthesized 0-13 MHz agile sinewave generator

A low-power monolithic 1 /spl mu/m CMOS IC generates a 26 MHz-wide single-sideband, frequency-hopped spread-spectrum waveform for wireless transmission in the 902-928 MHz unlicensed ISM band. A direct digital frequency synthesizer (DDFS) on this IC produces 10b samples of sine and cosine waveforms whose frequency is selected with an 11b input word, followed by an on-chip 10b D/A converter (DAC) to convert the DDFS output into a sampled-data analog signal. Simplifications in architecture and circuits reduce dissipation of this 2.9/spl times/4.9 mm/sup 2/ IC to 40 mW at 40 MHz with 3 V supply.<<ETX>>

A table lookup FET model for accurate analog circuit simulation

A table-based approach to the empirical modeling off FETs in circuit simulators addresses the specific requirements of analog circuit design, such as accuracy in reproducing small-signal parameters, large signal nonlinearities, subthreshold characteristics, substrate effects, short-channel effects, and voltage dependent capacitances. Efficiencies in storage and computation brought about by this model in SPICE considerably speed up circuit simulation, compared to an analytical model offering similar accuracy. Methods are described to extract the table entries. The model is not specific to any one type of device or technology, although examples are given of how it may be simplified by using physical insights into device operation. >