James Y. C. Chang

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-/spl mu/m CMOS. I. Architecture and transmitter design

A single-chip transceiver for frequency-hopped code division multiple access (CDMA) in the 900 MHz industrial, scientific and medical (ISM) band is implemented in 1-/spl mu/m CMOS. It combines a digital frequency synthesizer, a double quadrature upconverter, an integrated oscillator, and a power amplifier with variable output. Data modulates a carrier hopping at 20 kHz with quaternary frequency-shift keying (4-FSK). At an output power level of +3 dBm, the harmonics and spurious tones lie at -52 dBc or below. When active, the transmitter drains 100 mA from 3 V.

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-/spl mu/m CMOS. II. Receiver design

For pt. I see ibid., vol. 33, no. 4, April 1998. A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the data decisions. The received signal is dehopped when it is down-converted. The cascade noise figure is 8.6 dB, and the cascade IIP3 is -8.3 dBm. In active mode, the receiver takes 120 mA from 3 V.

The future of CMOS wireless transceivers

Building blocks alone do not account for the current interest in CMOS for RF applications. The more compelling reason is the opportunities CMOS affords for large-scale integration. Modern wireless transceivers will increasingly blend digital blocks into conventional analog front-ends for frequency synthesis, adaptivity, multi-mode operation, and sophisticated detection. This raises questions such as how well digital CMOS circuits can co-exist on the same substrate as the radio front-end, or whether there is sufficient on-chip isolation in a low-cost package to guarantee stable operation of a receiver with more than 100 dB of baseband gain, or how the power amplifier modulates the on-chip local oscillator. The future of CMOS transceivers may well depend on satisfactory answers to these questions. This paper presents design techniques to mitigate these problems in a single-chip 900 MHz spread-spectrum transceiver implemented in 1 /spl mu/m CMOS, and measurements of the transceiver to validate their effectiveness.

An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution PLL, and digital image rejection. To our knowledge this is the first reported multichannel broadband tuner embedded in a DOCSIS 3.0 System on a chip implemented in 65 nm pure digital CMOS technology.

An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.

A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 mm2 area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 mm2 area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.

An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0

The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput can be obtained by bonding together multiple downstream (DS) channels. This standard calls for the ability to bond any 4 channels in a 64MHz contiguous RF bandwidth. Solutions that allow even more channel bonding and provide more flexibility in the allocated frequency spectrum are preferred. This paper reports an embedded dual-tuner architecture able to select two independent 32MHz frequency bands, allowing for a maximum of 10 demodulated 6MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0MHz (CH 0), +6MHz (CH +1), +12MHz (CH +2), −6MHz (CH −1) and −12MHz (CH −2). Channels +1 and +2 lie at the images of channels −1 and −2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.

A 28 nm, 475 mW, and 0.4–1.7 GHz Embedded Transceiver Front-End Enabling High-Speed Data Streaming Within Home Cable Networks

A 28 nm CMOS software-defined transceiver (SDTRX) enabling high-speed data (HSD) streaming, including ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024-QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the-art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a digital-to-analog converter-based TX and a smart phase-locked loop system. It operates over 0.4–1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple transmitter (TX) to receiver (RX) loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia system-on-chip and is, to the authors’ knowledge, the first reported transceiver front-end to enable true HSD streaming within home cable networks.

A 180 mW multistandard TV tuner in 28 nm CMOS

A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7-13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.

A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver

We present a direct sampling full-band capture receiver for cable and digital TV applications. It consists of a 28nm CMOS ADC-based direct sampling receiver and a 0.18um BiCMOS LNA. It is capable of receiving 158 channels from 48MHz to 1000MHz simultaneously, achieving up to 10Gb/s data throughput, while exceeding DOCSIS requirements. The CMOS receiver occupies 1mm2 area while consuming 300mW. The LNA consumes 130mW. The total power dissipation from the receiver is 2.7mW per 6MHz channel.