Ahmed Ashry

A compact low-power UHF RFID tag

In this paper, the design of an ultra-low-power UHF RFID tag is introduced. The system architecture and the communication protocols are chosen to operate with the minimum requirements possible from the RFID tag. By moving most of system functionality to the RFID reader side, the circuit requirements of the RFID tag circuits are relaxed. Supply voltages for both analog and digital parts are chosen carefully for minimum power consumption. The RFID tag is designed in standard digital 0.13@mm CMOS technology. Simulations results of the main blocks are shown. The power consumption of the chip is only 1@mW, and the chip area is only 0.14mmx0.23mm.

A Simple and Accurate Model for RFID Rectifier

In this paper, a simple model for the UHF low power rectifier circuit is proposed. Using a novel approach to model the rectifier current waveform, simple analytical equations are derived. The output DC voltage and the efficiency of the rectifier are derived analytically. Simulation results of the rectifier using actual models are very close to those predicted by the proposed model. The derived formulas for the output DC voltage and the efficiency are simple and physically meaningful and can be used to optimize the performance of the rectifier.

A 4th Order 3.6 GS/s RF /spl Sigma//spl Delta/ ADC With a FoM of 1 pJ/bit

A 4th order RF LC-based ΣΔ ADC clocked at 3.6 GHz and centered at 900 MHz is presented. A simple design methodology is used to derive a robust architecture with a minimum number of feedback coefficients. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. An efficient algorithm for the tuning and calibration of the ΣΔ LC-based loop filter is also presented. The ADC, suitable for cognitive Software Defined Radio applications, is implemented in a standard 130 nm CMOS technology. It achieves a 52 dB SFDR and a 50 dB SNR in a 28 MHz BW and consumes only 15 mW from a 1.2 V supply. The Figure of Merit of the ADC is 1.0 pJ/bit, which is to date the best reported FoM for an RF ADC. The effect of the clock jitter on the ADC performance is also measured and presented.

Ultra low power UHF RFID tag in 0.13 μm CMOS

In this paper an ultra low power UHF RFID tag is introduced. By moving most of system functionality to the RFID reader side, the circuit requirements of the RFID tag circuits are relaxed. Supply voltages for both analog and digital parts are chosen carefully for minimum power consumption. The RFID tag is designed in standard digital 0.13 μm CMOS technology. Simulations results of the main blocks are shown. The power consumption of the chip is only 1 μW, and the chip area is only 0.14 mm x 0.23 mm.

Phase Noise Effect on Sine-Shaped Feedback DACs Used in Continuous-Time

Sine-shaped feedback DAC was proposed to be used in continuous-time ΣΔ ADCs for its immunity to clock jitter. However, in a sine-shaped DAC, the carrier is used as an analog signal to mix with the data, consequently, all the carrier noise appears in the sine-shaped data. The effect of carrier noise was studied before, but the analysis was based on the assumption of white noise, which is not true in real PLLs. In this work, we present a simple, intuitive, and accurate model that can predict the effect of the clock noise on the sine-shaped DAC. The model is generic and can be applied for any noise profile. We tried to keep it as close as possible to the noise profile of a real clock source. The analysis is verified by simulation and measurement results.

\Sigma\Delta

Sine-shaping of feedback DAC current in continuous-time ΣΔ ADCs is an effective solution to enhance their immunity to clock jitter. In this paper, a simple mixer circuit for producing a sine-shaped output in continuous-time ΣΔ ADCs is introduced. The proposed solution does not need extra clock source or synchronization circuit, as the mixer utilizes the same clock applied to the comparator. It is also shown the that the proposed circuit is immune to temperature and process variations. Simulation results of the proposed circuit implemented in 130nm CMOS process show good agreement with the expected results.

ADCs

In this paper, a simple and intuitive technique for analyzing clock jitter effect on bandpass Continuous-Time Sigma-Delta (ΣΔ) modulators is introduced. The power spectral density of the jitter noise for different feedback DAC shapes are derived and compared. It is shown that DAC output signal shapes used to reduce clock jitter sensitivity in lowpass Continuous-Time ΣΔ modulators may not be suitable for bandpass modulators.

Sine-shaping mixer for continuous-time ΣΔ ADCs

In this paper, a generic and simple approach to design Continuous-Time Sigma-Delta Modulators (CT ΣΔMs) based on Finite Impulse Response Digital-to-Analog Converter (FIR DAC) is introduced. The numerical conversion from Continuous-Time to Discrete-Time allows the designer to explore complex modulator architectures and different feedback DAC shapes, without dealing with difficult equations needed in other published design approaches.

Jitter analysis of bandpass continuous-time ΣΔMs for different feedback DAC shapes

In this paper, a fast and accurate technique for modeling and simulation of clock jitter in Continuous-Time sigma-delta (ΣΔ) modulators is introduced. In addition to its high speed compared to the traditional jitter simulation method, the proposed technique is still continuous-time based which is more convenient than discrete-time based jitter modeling suggested in other publications. Mathematical principle of the proposed technique as well as simulations results are presented and compared to other simulation techniques.

A generalized approach to design CT ΣΔMs based on FIR DAC

In this paper, the main defects of LC-based ΣΔ modulators due to process variations are presented. Resonance frequency shift of LC tank circuit, which was discussed is some publications, is shown to be one among many other possible defects that are discussed in this paper. The effect of each defect on modulator output spectrum is shown and discussed. It is suggested that the information extracted from the output spectrum can be used to calibrate the modulator main blocks.