Khaled Sharaf

A compact low-power UHF RFID tag

In this paper, the design of an ultra-low-power UHF RFID tag is introduced. The system architecture and the communication protocols are chosen to operate with the minimum requirements possible from the RFID tag. By moving most of system functionality to the RFID reader side, the circuit requirements of the RFID tag circuits are relaxed. Supply voltages for both analog and digital parts are chosen carefully for minimum power consumption. The RFID tag is designed in standard digital 0.13@mm CMOS technology. Simulations results of the main blocks are shown. The power consumption of the chip is only 1@mW, and the chip area is only 0.14mmx0.23mm.

A Simple and Accurate Model for RFID Rectifier

In this paper, a simple model for the UHF low power rectifier circuit is proposed. Using a novel approach to model the rectifier current waveform, simple analytical equations are derived. The output DC voltage and the efficiency of the rectifier are derived analytically. Simulation results of the rectifier using actual models are very close to those predicted by the proposed model. The derived formulas for the output DC voltage and the efficiency are simple and physically meaningful and can be used to optimize the performance of the rectifier.

A 12-mW Fully Integrated Low-IF dual-band GPS Receiver on 0.13-μm CMOS

This paper presents the design of a dual-band L1/L2 global positioning system (GPS) receiver. A low-IF architecture was used for dual-band operation with analog on-chip image rejection. The receiver is composed of dual-band LNAs and down-conversion mixers, a complex variable-gain channel select filter, analog AGC loop, and a 2-bit analog-to-digital converter. The receiver is to be integrated with a phase-locked-loop synthesizer designed in another work (Elesseily and Sharaf, 2006), The digital tracking correlator of the receiver is designed and implemented on FPGA. The acquistion part of the digital receiver is still under development using embedded software. The digital correlator showed successful operation with a signal of -30dB SNR at the A/D output. Designed in a 0.13 μm CMOS technology, the receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4.3 dB and 3.6 dB, and input compression points of -75 dBm and -78 dBm for L1 and L2 bands, respectively. The complex variable-gain channel select filter provides image rejection better than 25 dB and gain control range over 60 dB. The receiver consumes 12 mW from a 1.2-V supply.

CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers

Cell-based design using a new D-latch is employed to design a VCO and prescaler for RF PLL frequency synthesizers using a standard 0.5 /spl mu/m CMOS process and 3.3 V supply. The divide-by 64/65 dual-modulus prescaler has a maximum operating frequency of 1.6 GHz and dissipates 9 mW. The VCO is a single-stage ring oscillator with a maximum frequency of 2.2 GHz and consumes 20 mW. The VCO and prescaler combination operates at a maximum frequency of 1.6 GHz and consumes 56 mW.

The effect of electronic feedback on semiconductor lasers

Negative electronic feedback (EFB) has a strong effect on the performance of a bistable laser diode amplifier and on injection-locked lasers. Negative EFB drastically reduces the switching-up input power level and the hysteresis in the input-output power characteristic and in the tuning curves of the bistable laser amplifier. Furthermore, negative EFB leads to a reduction in the time delay associated with optical switching in diode laser amplifiers. This provides a means of enhancing the versatility of the proposed system in some potential applications. For an injected-locked laser, negative EFB achieves a broadening in the locking bandwidth and its dynamically stable region. >

An all-digital direct digital synthesizer fully implemented on FPGA

In this paper an all-digital pulse output direct digital synthesizer (DDS) is described. The synthesizer is fully implemented on FPGA and does not require any external analog components. Selective over-sampling and tapped delay line are used to reduce jitter and improve spectral performance. Selective over-sampling relaxes the requirements on the delay line with a minor effect on power consumption and circuit complexity. The delay line is implemented using the FPGA digital clock manager (DCM). The synthesizer generates clock signals with maximum output frequency up to fclk. It achieves sub-Hz resolution and sub-µs switching time. Experimental measurements validate system operation with spurious free dynamic range (SFDR) greater than 40 dB.

2-V, 1-GHz CMOS inductorless LNAs with 2-3 dB NF

Two 1 GHz single-stage single-ended low noise amplifiers (LNAs), requiring one external inductor and matched to 50 /spl Omega/ at both the input and output, have been designed using a 0.5 /spl mu/m CMOS technology. Both LNAs employ a cascode topology with a resistive pull-up load and with no on-chip inductor. The second topology uses an AC-coupled active-inductor load to provide more selectivity and reject the image channel. The LNAs have a gain greater than 10 dB at 1 GHz with a noise figure lower than 3 dB at a power dissipation of 17 mW from a 2 V supply. The inductor-less LNA has an IIP3 of -3.8 dBm compared to the active-inductor LNAs IIP3 of -21 dBm and their reverse isolation is higher than 45 dB.

Ultra low power UHF RFID tag in 0.13 μm CMOS

In this paper an ultra low power UHF RFID tag is introduced. By moving most of system functionality to the RFID reader side, the circuit requirements of the RFID tag circuits are relaxed. Supply voltages for both analog and digital parts are chosen carefully for minimum power consumption. The RFID tag is designed in standard digital 0.13 μm CMOS technology. Simulations results of the main blocks are shown. The power consumption of the chip is only 1 μW, and the chip area is only 0.14 mm x 0.23 mm.

Tail current flicker noise reduction in LC VCOs by complementary switched biasing

A new LC voltage-controlled oscillator circuit topology is proposed, in which the flicker noise generated by the tail transistor is noticeably reduced by utilizing the phenomenon of flicker noise intrinsic reduction due to switched biasing. A macro model of MOSFET under switched biasing is used to prove the idea. Circuit simulations are done on two oscillators with the same tail current value; one with fixed biasing and the other with the proposed switching. A 4 dBc/Hz phase noise improvement is achieved at 1 kHz frequency offset in the switched biasing scheme under the same power dissipation and tuning range.

The design and implementation of a bandpass GM-C filter for Bluetooth

In this paper, the design of a 14/sup th/ order Bandpass filter intended for low IF receiver (Bluetooth) is presented. The designed filter is fabricated in 0.6/spl mu/m CMOS DP 3M process. Measurements showed that the filter has 1.08MHz bandwidth, achieves 40dB stopband attenuation, and consumes 2.4mA from a 2.5V supply.