Amin Khajeh

E < MC2: less energy through multi-copy cache

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, which compromise cache reliability. We present Multi-Copy Cache (MC2), a new cache architecture that achieves significant reduction in energy consumption through aggressive voltage scaling, while maintaining high error resilience (reliability) by exploiting multiple copies of each data item in the cache. Unlike many previous approaches, MC2 does not require any error map characterization and therefore is responsive to changing operating conditions (e.g., Vdd-noise, temperature and leakage) of the cache. MC2 also incurs significantly lower overheads compared to other ECC-based caches. Our experimental results on embedded benchmarks demonstrate that MC2 achieves up to 60% reduction in energy and energy-delay product (EDP) with only 3.5% reduction in IPC and no appreciable area overhead.

Low-Power Multimedia System Design by Aggressive Voltage Scaling

Mobile multimedia systems are growing in complexity and scalability and, correspondingly, in their implementation challenges. By design, these systems have built-in error resilience that has been exploited in many different compression and transmission schemes mainly as a quality tradeoff. This paper proposes a paradigm shift in utilizing error resilience in an application-aware method for reducing the power consumption of memories in such systems by aggressively scaling the supply voltage beyond what is currently considered as ¿safe¿ operating conditions while maintaining performance. Results on H.264 decoders show that power savings of more than 40% are possible.

A combined channel and hardware noise resilient Viterbi decoder

Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the likelihood of the received data based on the distribution of the combined noise. Simulation results show a consistent improvement in BER performance across all SNRs with an area overhead ranging from 0.65% to 3.26% compared to the conventional Viterbi decoder when synthesized using a 65 nm standard library.

A Unified Hardware and Channel Noise Model for Communication Systems

This paper presents a single, scalable, unified statistical model that accurately reflects the impact of random embedded memory failures due to power management policies on the overall performance of a communication system. The proposed framework enables system designers to efficiently and accurately determine the effectiveness of novel power management techniques and algorithms that are designed to manage both hardware failure and communication channel noise, without the added cost of lengthy system simulations that are inherently limited and suffer from lack of scalability. Furthermore, the proposed framework facilitates performing both cross layer and intra layer tradeoffs where the faulty hardware can be treated as error-free hardware thus creating a much richer design space of power, performance and reliability.

A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment

This paper presents a novel approach to reduce power in multimedia devices. Specifically, we focus on JPEG2000 as a case study. This paper indicates that by utilizing the in-built error resiliency of multimedia content, and the disjoint nature of the encoding and decoding processes, ultra low power architectures that are hardware fault tolerant can be conceived. These architectures utilize aggressive voltage scaling to conserve power at the encoder side while incurring extra processing requirements at the decoder to blindly detect and correct for encoder hardware induced errors. Simulations indicate a reduction of up to 35% in encoder power depending on the choice of technology for a 65-nm CMOS process.

Cognitive Radio Rides on the Cloud

Cognitive Radio (CR) is capable of adaptive learning and reconfiguration, promising consistent communications performance for C4ISR1 systems even in dynamic and hostile battlefield environments. As such, the vision of Network-Centric Operations becomes feasible. However, enabling adaptation and learning in CRs may require both storing a vast volume of data and processing it fast. Because a CR usually has limited computing and storage capacity determined by its size and battery, it may not be able to achieve its full capability. The cloud2 can provide its computing and storage utility for CRs to overcome such challenges. On the other hand, the cloud can also store and process enormous amounts of data needed by C4ISR systems. However, todays wireless technologies have difficulty moving various types of data reliably and promptly in the battlefields. CR networks promise reliable and timely data communications for accessing the cloud. Overall, connecting CRs and the cloud overcomes the performance bottlenecks of each. This paper explores opportunities of this confluence and describes our prototype system.

Limits on voltage scaling for caches utilizing fault tolerant techniques

This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on standard benchmarks.

Power Management for Cognitive Radio Platforms

This paper discusses how the cognitive radio concept can be extended to allow the system not only to manage shared resources such as spectrum, but to use this knowledge to optimize the overall system power consumption. We introduce a case study of video over wireless via a 3G WCDMA modem connected to an H.264 decoder. We show that by utilizing knowledge about the communication channel, a savings of more than 20% of the overall system power is possible while maintaining a required quality of service.

Fast error aware model for arithmetic and logic circuits

As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability.

A Class of Low Power Error Compensation Iterative Decoders

Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders.