Ahmed Shebaita

Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT2, the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65-nm technology with VDD = 1 V, minimum size gate capacitance, Cg = 1.5 fF, and minimum size output capacitance, Co = 1 fF. Closed-form expressions that give the optimum threshold voltage and number of stages are presented.

Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers

This paper proposes a low power, low delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT2, the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively. Closed form expressions that give the optimum threshold voltage and number of stages are presented

FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling

This paper presents a framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced delay variations can no longer be ignored. Timing analysis considering coupling is iterative, and can have considerably larger run-times than a single pass approach. We propose a novel and accurate coupling delay model, and present techniques to increase the convergence rate of timing analysis when complex coupling models are employed. Experimental results obtained for the ISCAS benchmarks show promising accuracy improvements using our coupling model while an efficient iteration scheme shows significant speedup (up to 62.1%) in comparison to traditional approaches.

Including inductance in static timing analysis

In this paper analytical expressions are derived for effective load capacitances of RLC interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS gate. The new effective capacitance calculation technique poses no extra complexity as compared to the RC based approaches but can accommodate inductance. These new expressions are derived based on a generalized driving point admittance. The generalized driving point admittance takes inductance into consideration and hence accounts for the inductive shielding that in some cases can even exceed the resistive shielding in current technologies. Another improvement in the new effective capacitance calculation method is the utilization of a more general waveform shape that accounts for the non-monotonic behavior due to inductance effects. It is shown throughout the paper that two effective capacitances are required for accurate estimation of the propagation delay and rise time with an RLC interconnect load. Simulation results show that the error in propagation delays and rise times when neglecting inductance can be over 60% as compared to an RLC model in realistic interconnects. On the other hand, simulations show that the propagation delay and rise time maximum errors associated with the proposed approach are less than 10% as compared to SPICE.

A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis

A novel methodology for accurate and efficient static timing analysis is presented in this paper. Our methodology uses the traditional cell library table structure with one modification. The cell library tables are filled with the gate output signal moments instead of the gate output 50% delay and output slew. Using only few moments gives much better accuracy and visibility for the gate output waveform than using the time domain information. Simple convolution of the gate output moments with the interconnect moments yields the signal moments at the stage output. The parameters of the gate input signal, which are used for the table access of the successive stage, are directly computed from the predecessor stage output moments using the closed form expressions without having to explicitly transform the frequency domain moments to time domain. Thus, the interconnects and the gates are treated in a unified moment-based homogeneous framework. The proposed approach inherits the classical cell library tables approach efficiency with even reduced computation complexities. As compared to the classical cell library table approach, the proposed approach accounts for the increasingly nonlinear and non-monotonic waveform shapes which are prohibitively difficult to represent in the classical approaches. In contrary to the classical approaches, increasing the accuracy in the novel approach is made flexible and can be achieved by simply using more moments. To illustrate the concept and prove its merits, multiple examples are presented with 2-3 moments which maintain accuracy within 1%-3% as compared to SPICE.

Lower power, lower delay design scheme for CMOS tapered buffers

This paper proposes lower power, lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT2, the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65 nm technology with VDD=1V, minimum size gate capacitance, Cg=1.5fF, and minimum size output capacitance, C0=1fF. Closed form expressions that give the optimum threshold voltage and number of stages are presented.

A novel moment-based methodology for accurate and efficient static timing analysis

A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the load is very accurate. A gate and input capacitance characterization is proposed which provides for accuracy, efficiency and flexibility in the path performance calculation. To illustrate the concept and prove its merits, multiple examples are presented. The method is an order to two orders of magnitude faster than current source based one, while it maintains accuracy within 5% of SPICE.

FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis

This paper presents an algorithmic framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced delay variations can no longer be ignored. Timing analysis considering coupling is iterative, and can have considerably larger run-times than a single pass approach. We propose two different classes of coupling delay models: heuristic-based coupling model and current source-based coupling model, and present techniques to increase the convergence rate of timing analysis when such coupling models are employed. Our proposed coupling model show promising accuracy improvements compared to SPICE. Experimental results on ISCAS85 benchmarks validates the effec tiveness of our efficient iteration scheme. Our iteration algorithm obtained speedups of up to 62.1 % using a heuristic coupling model while 2.7 x using a current-based coupling model in comparison to traditional approaches.

An s-domain based framework for accurate and efficient static waveform analysis

A novel methodology for accurate and efficient static timing analysis is presented in this paper. The novel methodology uses the traditional cell library table structure with one modification, instead of filling the cell library tables with the 50% delay and slew of the gate output signal, the cell library tables are filled with the gate output signal moments. This approach eliminates the error due to the ramp approximation at the gate output which is based only on the 50% delay and slew. Simple convolution of the gate output moments by the interconnect moments yields the signal moments at the stage output. The parameters of the gate input signal, which are used for the table access of the successive stage, are directly computed from the predecessor stage output moments using closed form expressions. Thus, the interconnects and the gates are uniformly treated in a moment-based homogeneous framework. The novel approach inherits the classical cell library tables approach efficiency with even reduced computation complexities. As compared to the classical cell library table approach, the proposed approach accounts for the increasingly nonlinear waveform shapes and provides accuracy and flexibility in the path performance calculations. Increasing the accuracy in the novel approach is made flexible by simply using more moments. To illustrate the concept and prove its merits, multiple examples are presented with 2–3 moments which maintain accuracy within 1–3% versus 10–20% for the classical cell library table approach as compared to SPICE.

Expanding the frequency range of AWE via time shifting

The new technique of time shifted moment matching (TSMM) is introduced in this paper. The TSMM technique performs moment matching (for expansion around s = 0) on a time-shifted version of the original signal. As compared to other well-known techniques (such as AWE by Pillage and Rohrer, 1990), TSMM offers distinct advantages. The 50% delay and rise time are determined with much more accuracy for a given approximation order. Moreover, the solutions have significantly improved accuracy as compared to AWE, especially for moderate to highly inductive signals. TSMM is able to achieve the approximation capability of PVL (Feldmann and Freund, 1995) and PRIMA (Odabasioglu et al., 1998) with much lower approximation order.