Chirayu S. Amin

Statistical static timing analysis: how simple can we get?

With an increasing trend in the variation of the primary parameters affecting circuit performance, the need for statistical static timing analysis (SSTA) has been firmly established in the last few years. While it is generally accepted that a timing analysis tool should handle parameter variations, the benefits of advanced SSTA algorithms are still questioned by the designer community because of their significant impact on complexity of STA flows. In this paper, we present convincing evidence that a path-based SSTA approach implemented as a post-processing step captures the effect of parameter variations on circuit performance fairly accurately. On a microprocessor block implemented in 90nm technology, the error in estimating the standard deviation of the timing margin at the inputs of sequential elements is at most 0.066 FO4 delays, which translates in to only 0.31% of worst case path delay.

Weibull Based Analytical Waveform Model

Current CMOS technologies are characterized by interconnectlines with increased relative resistance w.r.t. driver outputresistance. Designs generate signal waveshapes that are verydifficult to model using a single parameter model such as thetransition time. In this paper, we present a simple and robustparameter analytical expression for waveform modeling based onthe Weibull cumulative distribution function. The Weibull modelaccurately captures the variety of waveshapes without introducingsignificant runtime overhead and produces results with less than5% error. We also present a fast and simple algorithm to convertwaveforms obtained by circuit simulation to the Weibull model. Amethodology for characterizing gates for the new model is alsopresented. Simulation results for many single and multiple inputgates show errors well below 5%. Our model can be used in amixed environment where some signals may still be characterizedby a single parameter.

Realizable RLCK circuit crunching

Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describes a method for realizable reduction of RLCK netlists by node elimination. The method is much faster than model order reduction technique and hence is appropriate as a pre-processing step. The proposed method eliminates nodes with time constants below a user specified time constants. By giving the freedom to the user to select a critical point in the spectrum of nodal time constants, this method provides an option to make a tradeoff between accuracy and reduction. The proposed method preserves the dc characteristics and the first two moments at all nodes. It also recognizes and eliminates all the redundant inductances generated by the extraction tools. The proposed method naturally reduces to TICER according to B. N. Sheehan (1999) in the absence of any inductances.

Efficient model order reduction including skin effect

Skin effect makes interconnect resistance and inductance frequency dependent. This paper addresses the problem of efficiently estimating the signal characteristics of any RLC network when skin effect is significant, which complicates interconnect simulation. In this paper, a new type of moments is defined that simplifies the interconnect simulation, namely, the square root moments. The time to calculate the square root moments is similar to the time to calculate the traditional moments, and the new moments preserve the recursive properties of the traditional moments. Hence, the method introduced here can handle the more complex problem of interconnect simulation with skin effect at almost no overhead compared to constant element interconnect simulation. Using the square root moments, higher order approximations can be reached as compared to traditional moments. Also, the PVL method is modified to implicitly match the square root moments. The simulation results reveal the high accuracy of the proposed methods as well as the apparent variation in the signal characteristics caused by skin effect.

Realizable reduction of interconnect circuits including self and mutual inductances

Reduction of an extracted netlist is an important preprocessing step for techniques such as model order reduction (MOR) in the design and analysis of very large scale integration circuits (VLSICs). This work describes a method for realizable reduction of extracted resistance-capacitance-inductance-mutual inductance netlists by node elimination. The method is much faster than MOR techniques and, hence, is appropriate as a preprocessing step. The proposed method eliminates nodes with time constants below a user-specified time constant. By giving the freedom to the user to select a critical point in the spectrum of nodal time constants, this method provides an option to make a tradeoff between accuracy and reduction. The proposed method preserves the dc characteristics and the first two moments at all nodes. It also recognizes and eliminates all the redundant inductances generated by the extraction tools. The proposed method naturally reduces to TICER (Sheehan, 1999) in the absence of any inductances.

Computation of signal-threshold crossing times directly from higher order moments

This paper introduces a simple method for calculating the times at which any signal crosses a prespecified threshold voltage (e.g., 10%, 20%, 50%, etc.) directly from the moments. The method can use higher order moments to asymptotically improve the accuracy of the estimated crossing times. This technique bypasses the steps involved in calculating poles and residues to obtain time-domain information. Once q moments are calculated, only 2q, multiplications and (q-1) additions are required to determine any threshold-crossing time at a vermin node. Moreover, this technique avoids other problem such as pole instability. The final outcome of this paper is a set of empirical expressions relating the moments to different threshold-crossing times in analogy to the t/sub d/=-0.693m/sub 1/ formula. The presented methodology can also be used with other user defined forms of empirical expressions relating the moments to different threshold-crossing times. Several orders of approximations an presented for different threshold-crossing times, depending on the number of moments involved. For example, the worst-case error of a first- to seventh-order (single to seven moments) approximation of 50% RC delay is 1650%, 192.26%, 11.31%, 3.37%, 2.57%, 2.56%, and 1.43%, respectively. This technique is very useful to obtain information about certain signal metrics, such as delay and rise time directly without having to compute the whole time domain waveform. In addition, if the whole waveform is required it can be easily determined by interpolation between different threshold-crossing points. The presented technique works for both step and nonstep inputs, including piecewise-linear waveforms.

Computation of signal threshold crossing times directly from higher order moments

This work introduces a simple method for calculating the times at which any signal crosses a pre-specified threshold voltage (e.g. 10%, 20%, 50%, etc.) directly from the moments. The method can use higher order moments to asymptotically improve the accuracy of the estimated crossing times. This technique bypasses the steps involved in calculating poles and residues to obtain time-domain information. Once q moments are calculated, only 2q multiplications and (q-I) additions are required to determine any threshold crossing time at a certain node. Moreover, this technique avoids other problems such as pole instability. Several orders of approximations are presented for different threshold crossing times depending on the number of moments involved. For example, the worst case error of a first to a seventh order (single to seven moments) approximation of 50% RC delay is 1650%, 192.26%, 11.31%, 3.37%, 2.57%, 2.56%, and 1.43%, respectively. If the whole waveform is required it can be easily determined by interpolation between different threshold crossing points. The presented technique works for RC circuits for both step and nonstep inputs, including piecewise linear waveforms.

Realizable reduction of RLC circuits using node elimination

Reduction of an extracted netlist is an important step in the design and analysis of VLSI circuits. This paper describes a method for realizable reduction of extracted RLC netlists by node elimination. The proposed method eliminates nodes with time constants below a user specified time constant. By giving the freedom to the user to select a critical point in the spectrum of nodal time constants, this method provides an option to make a trade off between accuracy and reduction. The proposed method preserves the dc characteristics and the first two moments at all nodes. It also recognizes and eliminates all the redundant inductances generated by the extraction tools. The proposed method naturally reduces to TICER in the absence of any inductances.

Expanding the frequency range of AWE via time shifting

The new technique of time shifted moment matching (TSMM) is introduced in this paper. The TSMM technique performs moment matching (for expansion around s = 0) on a time-shifted version of the original signal. As compared to other well-known techniques (such as AWE by Pillage and Rohrer, 1990), TSMM offers distinct advantages. The 50% delay and rise time are determined with much more accuracy for a given approximation order. Moreover, the solutions have significantly improved accuracy as compared to AWE, especially for moderate to highly inductive signals. TSMM is able to achieve the approximation capability of PVL (Feldmann and Freund, 1995) and PRIMA (Odabasioglu et al., 1998) with much lower approximation order.

Modeling unbuffered latches for timing analysis

Unbuffered latches are often used in high-performance designs with custom timing flows. Adding these circuits to a standard library enables improved designs without blowing the library size. We observe a high potential frequency gain (up to 16%) for smaller power consumption. Accurate models for static timing analysis are required to reach a good point on the safety to performance trade-off. We are proposing a complete modeling methodology that can fit in a standard timing analysis flow. An accurate n-model is presented for the input impedance of an unbuffered latch with less than 2% error. We also present a new setup criteria required for these latches. We also show that more advanced waveform models are required to model the output. A Weibull waveform model proves to be effective in this case.