Aida Todri

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

3-D integration presents a path to higher performance, greater density, increased functionality and heterogeneous technology implementation. However, 3-D integration introduces many challenges for power and thermal integrity due to large switching currents, longer power delivery paths, and increased parasitics compared to 2-D integration. In this work, we provide an in-depth study of power and thermal issues while incorporating the physical design characteristics unique to 3-D integration. We provide a qualitative perspective of the power and thermal dissipation issues in 3-D and study the impact of Through Silicon Vias (TSVs) size for their mitigation. We investigate and discuss the design implications of power and thermal issues in the presence of decoupling capacitors, TSV/on-die/package parasitics, various resonance effects and power gating. Our study is based on a ten-tier system utilizing existing 3-D technology specifications. Based on detailed power distribution and heat dissipation models, we present a comprehensive analysis of TSV tapering for alleviating power and thermal integrity issues in 3-D ICs.

Power supply noise aware workload assignment for multi-core systems

As the industry moves from single- to multi-core processors, the challenges of how to reliably design and analyze power delivery for such systems also arise. We study various workload assignments to cores and their impact on the global power grid noise. We develop metrics to estimate the amount of noise propagated from core to core and propose a power supply noise aware workload assignment method. In our experiments, we show that performance loss can be significant if workload assignment is not properly made.

Testing a Commercial MRAM Under Neutron and Alpha Radiation in Dynamic Mode

Academic and industrial research interest in terrestrial radiation effects of electronic devices has expanded over the last years from avionics and military applications to commercial applications as well. At the same time, the need for faster and more reliable memories has given growth to new memory technologies such as Magnetic (magneto-resistive) Random Access Memories (MRAM), a promising new non-volatile memory technology that will probably replace in the future the current SRAM and FLASH based memories. In this paper, we evaluate the soft error resilience of a commercial toggle MRAM in static and dynamic test mode, under neutron radiation with energies of 25, 50 and 80 MeV as well as under a Californium (Cf-252) alpha source.

Multiple Cell Upset Classification in Commercial SRAMs

While single bit upsets on memories and storage elements are mitigated with either the use of redundancy and/or error correction codes, Multiple-Cell-Upsets (MCU) may become a significant threat to the integrity of systems when the corrupted cells belong to the same word. In this paper, we identify four types of MCUs as they were recorded during several irradiations under an atmospheric-like neutron beam (ISIS facility). An analysis is done on the underlying reasons of occurrence of each MCU type, as well as their shapes and sizes in order to classify them. The results of this work concern a commercial 90 nm SRAM that was tested under an atmospheric neutron beam in static and dynamic mode. It is shown that, when the memory is in dynamic mode, not only the typical MCUs that involve a few flipped cells may appear but also large clusters of upsets are possible to occur with hundreds or even thousands of cells being affected.

A pseudo-dynamic comparator for error detection in fault tolerant architectures

Although CMOS technology scaling offers many advantages, it suffers from robustness problem caused by hard, soft and timing errors. The robustness of future CMOS technology nodes must be improved and the use of fault tolerant architectures is probably the most viable solution. In this context, Duplication/Comparison scheme is widely used for error detection. Traditionally, this scheme uses a static comparator structure that detects hard error. However, it is not effective for soft and timing errors detection due to the possible masking of glitches by the comparator itself. To solve this problem, we propose a pseudo-dynamic comparator architecture that combines a dynamic CMOS transition detector and a static comparator. Experimental results show that the proposed comparator detects not only hard errors but also small glitches related to soft and timing errors. Moreover, its dynamic characteristics allow reducing the power consumption while keeping an equivalent silicon area compared to a static comparator. This study is the first step towards a full fault tolerant approach targeting robustness improvement of CMOS logic circuits.

Through-Silicon-Via resistive-open defect analysis

Three-dimensional (3D) integration is a fast emerging technology that offers integration of high density, fast performance and heterogeneous circuits in a small footprint. Through-Silicon-Vias (TSVs) enable 3D integration by providing fast performance and short interconnects among tiers. However, they are also susceptible to defects that occur during manufacturing steps and cause crucial reliability issues. In this paper, we perform an analysis of resistive-open defects (ROD) on TSVs considering coupling effects (i.e. inductive and capacitive) and a wide frequency spectrum. Our experiments show that both substrate coupling and switching frequency can have a significant impact on weak open TSV behavior.

Low-power SRAMs power mode control logic: Failure analysis and test solutions

Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected from the power supply during a long period of inactivity, thus reducing static power consumption. This paper focuses on low-power SRAMs, and in particular, the power gating mechanisms of core-cells and peripheral circuitry. We provide a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic. Based on this analysis, we introduce appropriate fault models that represent the observed faulty behaviors. Finally, we propose an efficient test solution targeting the set of identified fault models.

A study of decoupling capacitor effectiveness in power and ground grid networks

Decaps can be very effective in reducing power grid noise, but they cannot be inserted on a chip in an ad-hoc manner without considering the grid parasitic impedances, switching frequencies of the blocks, and proximity to the power supply pins. It is possible that a decoupling capacitor inserted into a vacant space left by a placer may not only be inefficient, but can also be detrimental. In this paper, we present a detailed study of the decoupling capacitors effectiveness in the uniform RLC power and ground grid networks. Based on the analysis of a simple circuit in which the decoupling capacitor amplifies the power grid noise, we explain why a decap can be detrimental. We introduce effectiveness metrics for determining those decoupling capacitor locations that capture the effects of parasitic impedances between the decap and switching circuit, decap and power supply, and switching frequency and magnitude of the switching circuit. Our experimental results demonstrate the effectiveness of the proposed metrics.

Analysis and optimization of power-gated ICs with multiple power gating configurations

Power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. Disconnecting gated blocks causes changes in densities of currents flowing through a grid. Even in DC conditions, current densities in some grid branches may increase for some gating configurations to the extent of violating electromigration (EM) constraints. The existing DC methods for grid sizing optimize the grid area under voltage drop (IR) and EM constraints for one configuration of circuit blocks connected to the grid. We show that these methods cannot be directly applied for optimizing power-gated grids. We analyze the effects of EM and IR voltage drop in power grids with multiple power gating configurations. Based on our analyses, we develop a grid sizing algorithm to satisfy all reliability constraints for all feasible gating configurations. Our experimental results indicate that a grid initially sized for all blocks present may be modified to fulfill EM and IR constraints for multiple gating schedules with only a small area increase.

Evaluation of test algorithms stress effect on SRAMs under neutron radiation

Electronic system reliability over soft errors is very critical as the transistor size shrinks. Many recent works have defined the device error rate under radiation for SRAMs in hold mode (static) and during operation (dynamic). This paper evaluates the impact of running test algorithms on SRAMs exposed to neutron radiation in order to define their stressing factor. The results that we show are based on experiments performed at the TSL facility in Uppsala, Sweden using a Quasi-Monoenergetic neutron beam. The evaluation of the test algorithms is based on the calculated device SEU cross section.