Aimen Bouchhima

Programming models and HW-SW interfaces abstraction for multi-processor SoC

For the design of classic computers the parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels are needed. For the long term, the use of higher level programming models open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs

Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC

At high abstraction level, multi-processor system-on-chip (SoC) designs are specified as assembling of IPs which can be hardware or software. The refinement of communication between these different IPs, known as hardware/software interfaces, is widely seen as the design bottleneck due to their complexity. In order to perform early design validation and architecture exploration, flexible executable models of these interfaces are needed at different abstraction levels. In this paper, we define a unified methodology to implement executable models of the hardware/software interface based on SystemC. The proposed formalism based on the concept of services gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling at the transaction accurate level is presented. Experimental results show that this method allows higher simulation speed with early performance estimation.

Automatic instrumentation of embedded software for high level hardware/software co-simulation

We propose an automatic instrumentation method for embedded software annotation to enable performance modeling in high level hardware/software co-simulation environments. The proposed “cross-annotation” technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level. Thus, target and annotated native binaries are guaranteed to have isomorphic control flow graphs (CFG). The proposed method takes into account the processor-specific optimizations at the compiler level and proves to be accurate with low simulation overhead.

Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model

In this paper, we propose a methodology to perform early design stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS abstraction level and a HW Platform described at an arbitrary abstraction level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an early design stage before the system design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).

Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer

As a fast and accurate SW simulation model, we present a model called fast timed SW model. The model enables fast simulation by native execution of application SW and OS. It gives simulation accuracy by timed SW and HW simulation. When building fast timed SW models, we need to solve two problems: (1) how to enable timing synchronization between the native execution and HW simulation and (2) how to obtain the portability of native execution (that needs multi-tasking from simulation environments to emulate its multi-tasking operation) on different simulation environments (that give different types of multi-tasking). In this paper, to enable the synchronization, we present a synchronization function. To enable the portability, we present an adaptation layer called simulation environment abstraction layer. We present our case studies in building fast timed SW models.

Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration

Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity. In this paper, we describe an abstract, high level CPU subsystem model that captures the specificities of such MP-SoC architectures, along with a timed co-simulation environment to perform early exploration of the entire HW/SW design. The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems. Experimentation with a MPEG4 application proves the interest of the proposed methodology.

Validation in a component-based design flow for multicore SoCs

Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable this integration, we use a design approach called component based-design approach. In this approach, the validation of system integration takes most of design efforts. This paper presents an automatic method of SoCs design validation. Based on a generic simulation wrapper architecture, the presented method provides automatic generation of executable models throughout different stages of SoC design flow. A case study of validating a VDSL application shows the effectiveness of the method.

High-level architecture exploration for MPEG4 encoder with custom parameters

This paper proposes the use of a high-level architecture exploration method for different MPEG4 video encoders using different customization parameters. The targeted architecture is a heterogeneous MP-SoC which may include up 2 coarse grain SIMD (task level SIMD) subsystems to perform the computations. The customization parameters are related to video resolution, frame rate, communication network, level of parallelism and CPU types. These parameters are determined during the high-level architecture exploration, by estimating the architecture performances at early stages of the design flow. Experiments shows that the error factor of these high-level performances estimations are less than 10% compared to those obtained with final manually implemented RTL architecture. This method was used successfully for exploration of different MPEG4 architecture configurations with different customization parameters. We consider these experiments a breakthrough because they show how a complex design can be mastered through a set of pragmatic choices.

Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces.

A unified HW/SW interface model to remove discontinuities between HW and SW design

One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model HW/SW interface twice. Using two separate models introduces a discontinuity between hardware and software. This paper introduces a unified HW/SW component model to describe different parts of HW/SW interface at different abstraction levels. The benefits of using the proposed model are two fold: first, it provides a single model to present system design from abstract specification to mixed HW/SW implementation and second, it enables full system simulation at different abstraction level during refinement flow.