Patrice Gerin

Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC

At high abstraction level, multi-processor system-on-chip (SoC) designs are specified as assembling of IPs which can be hardware or software. The refinement of communication between these different IPs, known as hardware/software interfaces, is widely seen as the design bottleneck due to their complexity. In order to perform early design validation and architecture exploration, flexible executable models of these interfaces are needed at different abstraction levels. In this paper, we define a unified methodology to implement executable models of the hardware/software interface based on SystemC. The proposed formalism based on the concept of services gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling at the transaction accurate level is presented. Experimental results show that this method allows higher simulation speed with early performance estimation.

Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures

In this paper, we present a cosimulation environment that provides modularity, scalability, and flexibility in cosimulation of SoC designs with heterogeneous multi-processor target architectures. Our cosimulation environment is based on an object-oriented simulation environment, SystemC. Exploiting the object orientation in SystemC representation, we achieve modularity and scalability of cosimulation by developing modular cosimulation interfaces. The object orientation also enables mixed-level cosimulation to be easily implemented thereby the designer can have flexibility in trade off between simulation performance and accuracy. Experiments with an IS-95 CDMA cellular phone system design show the effectiveness of the cosimulation environment.

Automatic instrumentation of embedded software for high level hardware/software co-simulation

We propose an automatic instrumentation method for embedded software annotation to enable performance modeling in high level hardware/software co-simulation environments. The proposed “cross-annotation” technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level. Thus, target and annotated native binaries are guaranteed to have isomorphic control flow graphs (CFG). The proposed method takes into account the processor-specific optimizations at the compiler level and proves to be accurate with low simulation overhead.

On MPSoC Software Execution at the Transaction Level

This article presents a wide variety of techniques for realizing transaction-level models of the increasingly large-scale multiprocessor systems on chip. It describes how such models of hardware allow subsequent software integration and system performance evaluation.

Native MPSoC co-simulation environment for software performance estimation

Performance estimation of Multi-Processor System-On-Chip (MPSoC) at a high abstraction level is required in order to perform early architecture exploration and accurate design validations. Although abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue - Native software simulation, a good candidate from the speed point of view, suffers from this issue. In this paper, we present a transactional level simulation environment that allows reliable performance estimation with a specific focus on software timing estimation on multi processor architectures. The embedded software is compiled natively on the host running the simulation and instrumented to reflect its execution on a specific target processor and then executed on a simulation model of the underlying hardware. The key contribution of this work is the use of both static and dynamic analysis, that allow realistic timing measurements in native software simulation. Experimental results show the efficiency of the proposed method to accurately estimate software performance in co-simulation environments.

Efficient implementation of native software simulation for MPSoC

Efficient and precise simulation models at a high abstraction level are required in order to perform early design validations and architecture explorations of multi- processor system-on-chip (MPSoC) platforms. Although native software simulation approaches provide interesting capabilities, they quickly become unsuitable when complex hardware architecture have to be considered. In this paper, we present a SystemC-based MPSoC platform implementation that allows native software simulation while keeping details of the underlying hardware model. The key contribution of this work is a realistic memory mapping modelling that makes possible the simulation of operating systems and software applications on complex hardware models with multiple processors and DMA devices. This method also allows the reuse of different software components for the target processor(s). Experimental results show the efficiency of the proposed method to validate software on complex hardware architectures.

Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels

Configurable processors are adopted by several latest embedded system projects to make use of application specific custom instructions for instruction level parallelism. Meanwhile, designers also use multiple processors for thread level parallelism. Configurable heterogeneous multi-processor system-on-chip (CH-MPSoC) has both parallelism advantages and seems to be a good solution for future embedded systems. Because CH-MPSoC has lots of architectural parameters, new design methodologies are required to help exploring this huge design space and finding a suitable solution for all user-defined constraints. We propose a new exploration flow using a budget based problem partitioning approach integrated with multiple abstraction levels. By using several abstraction levels, global budgets of speed, power and cost can be decomposed into detailed ones which are mapped onto each component. One special abstraction level called transaction accurate level is used in our flow to model both multi-processor architectures and configurable processors. At this level, hardware tasks and peripherals use transaction level modeling to achieve high simulation speed. Statistic information of configurable processors is abstracted and annotated to each software tasks. The execution results are used to adjust budgets and guide automatic extended instructions generation. With the Motion-JPEG case study, we illustrate detailed advantages of our CH-MPSoC exploration flow.

Modelling and architecture exploration of a medium voltage protection device

In this paper we focus on the modelling and architecture exploration of Schneider Electric protection devices at the Cycle Accurate Bit Accurate (CABA) level. The goal is to find the best hardware/software partitioning and improve the tests coverage rate in order to increase the robustness and fault-tolerance of this class of safety devices. This approach is applied on a medium voltage protection relay called Sepam10. This example is considered to be typical for a wide class of devices, thus showing that the modelling approaches used in high complexity System On Chip (SoC) devices are also of great interest for power electronic control devices.

On Software Simulation for MPSoC

The performance estimation of applications running on Multi-Processor System-On-Chip (MPSoC) is required to perform software and hardware design choices and design validations. As cycle accurate simulation is very time consuming, and may have a level of accuracy that is not always needed, simulation at higher levels of abstraction is recognized as a way to perform early validation of software. Although even very abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue.

A Unified HW/SW Interface Refinement Approach for MPSoC Design

We introduce the service based component model as a unifying concept to specify and refine the HW/SW interface in MPSoC designs. The model allows encompassing the intricate dependencies between hardware components and low level system software in a structured, component based approach. Based on this model, we propose a method and tools to automate the refinement of abstract HW/SW interfaces using a predefined component library. The main benefit of such refinement methodology is a seamless HW/SW integration allowing efficient customization of the HW/SW interface. The approach was successfully applied to the design of an MPEG-4 video encoder