Aixi Zhang

Numerical study on nanowire tunnel FET with dynamic threshold operation architecture

In this paper, a nanowire tunnel field-effect transistor with dynamic threshold operation architecture (DT-NTFET) is proposed and the numerical study on its characteristics is presented. It shows that, in DT operation, the DT-NTFET can choose the threshold voltage (VT) flexibly by changing the adjust gate voltage, thus it can be applied as a multifunctional device in the future circuit design; in common mode operation, its subthreshold swing (SS) gets steeper, and its drive current is enhanced with no loss of OFF-state current.

Numerical study on effects of random dopant fluctuation in double gate tunneling FET

Impacts of random dopant fluctuations (RDFs) on the performance of an optimized double-gate (DG) tunneling FET (TFET) are studied using 3-D device simulations. The sensitivity of the TFET performance with a high-k gate dielectric to RDF is explored in this paper. Sanos approach is used to generate random doping profiles for statistical device simulation. It is found that TFET suffers from dramatic shift and fluctuations in electrical parameters (Vth, gm and SS for instance) due to RDF, thus emerging a further impact on circuit performance.

Field-based parasitic capacitance models for 2D and 3D sub-45-nm interconnect

In the design of scaling complementary metal-oxide-semiconductor (CMOS), back-end-of-the-line (BEOL) interconnection becomes a limiting factor to circuit performance. Compact models for paratactic capacitance, which are scalable with wire geometries, are desired for circuit simulation and design. Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. The solution can be easily extended to the case of two parallel wires. Its physical base minimizes the complexity and error comparing with a traditional model fitting process. The new compact model has been verified with COMSOL simulations. It accurately predicts the capacitance for not only the nominal wire dimensions from the latest ITRS updates, but also for a wide range of other BEOL wire dimensions.

A field-based parasitic capacitance model with 3-D terminal and terminal fringe components

In this paper, a parasitic capacitance model for a single three-dimensional (3-D) wire above a plate is developed. The model decomposes electric field into various regions and gives solutions to each part. The total capacitance is the summation of all capacitance parts corresponding to the electric field distribution. The models physical base minimizes its complexity and error comparing to a traditional empirical fitting process. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of BEOL wire dimensions. Thus, it holds potential to be further investigated for circuit simulation and design.