Ajay Khoche

Packet-based input test data compression techniques

This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The technique is based on grouping data packets and applying various binary encoding techniques, such as Huffman codes and Golomb-Rice codes. Experiments on actual industrial designs and benchmark circuits show an input vector data reduction ranging from 17/spl times/ to 70/spl times/.

Test economics for multi-site test with modern cost reduction techniques

Test approaches that can be combined with multisite, like reduced pin-count test, low channel cost ATE, and bandwidth matching, are becoming pervasive. Yet their economic benefits, the tradeoffs, and the long-term scalability of their benefits during technology progress, are not well understood In this paper the benefits and tradeoffs will be analyzed using technical cost modeling. The dependency of the benefits on the application are analyzed by modeling the test cost for 4 different applications. It is shown that the mentioned test approaches can result in a significant and scalable reduction of the Cost of Test.

A new methodology for improved tester utilization

Typically the DFT features are decided during the design and remain fixed after the design is completed. This makes a device testable only on ATEs, which can satisfy the test requirements for that chip. If such an ATE is not available then the IC either cannot be fully tested, or ATE resources are wasted when it is designed for less capabilities. This paper presents a methodology that builds on the tester retargetable pattern technology for testing ICs on testers with different pin capabilities. Such a capability would be an essential element in reduced pin-count (multi-site) testing. The interfacing needs between the Test Automation World and the Tester Environment are also developed in this paper.

Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits

This paper will propose an overall portfolio of different modern test techniques, like reduced pin-count test, SoC multi-site test, low channel cost ATE, test vector compression, bandwidth matching, and advanced probing technologies, to lower the cost of test. The overall economic benefits, the potential synergies, the overall tradeoffs, and the scalability of the benefits of these techniques, are complex to understand and currently not well understood. This problem will be analyzed in this paper by using technical cost modeling. The dependency of the benefits on different applications will be analyzed by modeling the test cost for four different applications. It will be shown that the right match between the application and a combination of the described techniques can result in a significant reduction of the cost of test. Moreover, it will be shown that this optimal match evolves during technology progress and can enable a scalable reduction of the cost of test.

FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System

This article discusses the embedding of a tester on an FPGA, which uses IJTAG to enable flexible and dynamic access to test configurations of the on-chip instruments.

System-in-Package is Coming to Consumer Products: Is Test Ready?

SiP enables integration of heterogeneous technologies like RF, memory, analog and passives (RLC) into one package, which otherwise is very difficult, if not impossible, to do on a single die. This property of SiP has allowed it to become a viable and accepted complement to system-on-a-chip (SoC) in reducing physical volume, weight, and power consumption; characteristics that are especially valuable for portable, personal electronics. Examples of these products are cellular telephones, personal digital assistants, music players, global positioning systems, digital cameras, and combinations thereof. The fact, that portable personal electronics is one of the fastest growing markets, draws the industry’s attention to any problems in its way.