Jochen Rivoir

Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration

Precise and fast time measurements have many applications in tests. An ATE that integrates a general purpose time-to-digital converter (TDC) into each pin benefits from a fully digital implementation and autonomous calibration. This paper presents two novel calibration methods and supporting HW for a vernier delay line (VDL) based TDC. A novel linearity calibration uses the deviation from a uniform code density, when measuring a large number of uncorrelated events from a local ring oscillator. A novel coarse/fine calibration corrects for supply voltage induced delay fluctuations by injecting a known time interval into the VDL after each measured event. Design parameters for 90 nm CMOS are described. SPICE and MATLAB simulations and a detailed statistical analysis indicate post calibration errors of 2 ps RMS with unlimited dynamic range, at sample rates of 100 Msa/s

Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator

Precise and fast time measurements have many applications in test that can be covered cost effectively by vernier delay line (VDL) based time-to-digital converters (TDC), implemented fully digitally in a modern CMOS process. Their inherent nonlinearity can be measured using a statistical code density method that relies on uniformly distributed time events. This paper discusses using a simple free-running ring oscillator with a choice of oscillation periods to generate sufficiently uniformly distributed calibration events. The uniformity requirement is shown to exclude a huge number of small oscillation period ranges, which are too coherent with the TDCs internal clock. A simple algorithm for checking suitability of a randomly chosen period from a non-perfectly stable, jittered ring oscillator is presented. Number and size of suitable period ranges are given analytically. For a VDL-based TDC design in 90 nm CMOS, a sufficiently large range of suitable oscillation periods will on average found after the third try; under worst case conditions with 99.99% confidence after trying 256 period choices. The proposed method enables TDCs with digital-only, fully autonomous calibration

On the use of standard digital ATE for the analysis of RF signals

In this paper, we investigate the use of standard digital ATE for the analysis of FM-modulated RF signals. The key idea is to use the 1-bit digitizer of a digital test channel in order to convert the frequency information contained in a FM-modulated signal into a timing information contained in a digital bit stream; a post-processing algorithm based on the concept of zero-crossing detection is then employed to retrieve this information. Coherent under-sampling is exploited to extend the capabilities of test equipment with a limited sampling frequency for the analysis of high-frequency signals. The proposed approach is evaluated on two different case studies related to LTE and GSM communication standards. Both simulation and hardware experiments are presented to demonstrate the viability of the technique.

Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE

This paper presents a reconstruction technique based on zero-crossing detection that permits analyzing FM-modulated signals using digital ATE channels. The technique relies on sampling of the analog/RF signal through a 1-bit comparator and the post-processing of the resulting bit stream. The proposed solution is validated through both simulation and hardware experiments.

Level-crossing based QAM demodulation for low-cost analog/RF testing

This paper concerns production test of analog and RF communication devices. The use of standard digital tester channel for the acquisition of modulated analog/RF signals is investigated in order to implement low-cost functional test. The idea is to use the comparator available in a standard digital test resource to record level-crossing events on a signal coming from the device under test, and then to apply a dedicated algorithm to retrieve the signal information. The proposed method is evaluated through both simulation and hardware experiments using the popular QAM coding scheme that combines both amplitude and phase shift-keying. The approach is generic and can be applied to a broad range of modulation schemes.

A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources

The test of analog & RF circuits at wafer-level suffers from both quality and throughput limitations, especially due to probing issues and limited count of expensive instrumentation resources. Since final test after packaging guarantees product performances, constraints on wafer-level test can be relaxed. This paper investigates a signal acquisition protocol based on the use of digital tester channels to perform the demodulation of analog/RF signals. Due to the large availability of such hardware resources on most testers, this approach allows to setup a multi-site strategy, thus increasing the test throughput. The fundamental concept is to capture the signal through the 1-bit comparator available in a digital tester channel and to process the resulting bit stream to retrieve the analog/RF signal characteristics. In this paper, the proposed solution is illustrated for the demodulation of Frequency-Modulated (FM) and Amplitude-Modulated (AM) signals. Both simulation and experimental results obtained with a Verigy 93K platform are presented.

AM-demodulation of analog/RF signals using digital tester channels

This paper investigates a signal acquisition protocol based on level-crossings that permits the demodulation of AM analog/RF signals using only standard digital ATE. The fundamental concept is to capture the signal through the 1-bit comparator available in digital tester channels and to process the resulting bit stream to retrieve the analog/RF signal characteristics. The proposed solution is evaluated through both simulation and hardware experiments.

We Need Faster & Deeper Scan and More Realistic Tests

A hundredfold increase of scan data volume has been predicted for the next ten years. This position statement discusses the implications on ATE and EDA, within the constraints of test cost, quality, and time-to-market. The first conclusion will be that the demand for more scan data can be met without increasing test cost, by exploiting test data sharing across multiple equal cores, relying on improved test data compression, and on faster scan I/O, served by deeper ATE memory. But will this provide sufficient test coverage? It seems too challenging to create effective, up-to-date fault models and suitable scan test conditions such that practical ATPG alone can successfully target all defects in future complex heterogeneous SiP and 3D packages. Additional new test methodologies will be needed to test devices under stressful realistic conditions. ATE must provide well controllable stress test conditions and interact with the DUT at a higher level of abstraction to enable fast development of system-like tests.

Protocol-Aware ATE enables cooperative test between DUT and ATE for improved TTM and test quality

Coverage gaps in structural test for 65 nm can be filled with functional test that is however hindered by non-deterministic device behavior and limited access into complex autonomous SoCs. Protocol-aware ATE can tolerate non-deterministic device responses and interact intelligently with the device (CPU and DFT) through a host interface. This enables an efficient cooperative test between DUT and ATE, leveraging comprehensive access of an on-chip CPU, and the SW to do so from design verification. Such cooperative test is highly portable (TTM), realistic (test quality), and fast (cost of test). In case the SoC or SiP lacks memory for the on-chip CPU, ATE could emulate missing memories to enable a functional operation of the CPU. However, roundtrip times between DUT and ATE imply long latencies that make test less realistic and must be accommodated for by DFT in the memory controller.

Experiments on the analysis of phase/frequency-modulated RF signals using digital tester channels

This paper presents experiments around the analysis of phase/frequency-modulated signals using digital ATE channels. Based on the concept of zero-crossing detection, the proposed technique relies on the sampling of the analog/RF signal through a 1-bit comparator and the post-processing of the resulting bit stream. Coherent under sampling is used to extend the application range of the method, allowing the analysis of high-speed analog signals using standard test equipment operating with a limited sampling frequency. Simulation results show the viability of the technique. Hardware experiments are presented, which are in good agreement with simulation results.