Erik H. Volkerink

Packet-based input test data compression techniques

This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The technique is based on grouping data packets and applying various binary encoding techniques, such as Huffman codes and Golomb-Rice codes. Experiments on actual industrial designs and benchmark circuits show an input vector data reduction ranging from 17/spl times/ to 70/spl times/.

Delay defect screening using process monitor structures

This paper presents delay test data collected from test chips fabricated in a 0.18 /spl mu/ technology. The experimental data shows that process monitor structures such as on-chip ring oscillators are effective in identifying slow parts while performing transition fault testing at frequencies slower than the rated frequency.

Test economics for multi-site test with modern cost reduction techniques

Test approaches that can be combined with multisite, like reduced pin-count test, low channel cost ATE, and bandwidth matching, are becoming pervasive. Yet their economic benefits, the tradeoffs, and the long-term scalability of their benefits during technology progress, are not well understood In this paper the benefits and tradeoffs will be analyzed using technical cost modeling. The dependency of the benefits on the application are analyzed by modeling the test cost for 4 different applications. It is shown that the mentioned test approaches can result in a significant and scalable reduction of the Cost of Test.

Efficient seed utilization for reseeding based compression [logic testing]

The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum number of specified bits in a test pattern belonging to a given test set. However, for most practical designs the majority of test patterns have significantly fewer specified bits compared to the maximum. This limits the amount of compression that can be achieved with conventional reseeding. This paper presents a new reseeding technique that overcomes this problem by generating a single test pattern from multiple seeds and multiple test patterns from a single seed. The new reseeding technique is applied to two industrial designs, resulting in significant reduction in tester memory requirement and test application time compared to the conventional reseeding technique.

Tackling test trade-offs from design, manufacturing to market using economic modeling

This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions that include test time, die area, yield, time-to-market, and engineering effort. It allows one to forecast how those test approaches scale with technology progress. The economic models are modular and expandable. The modeling methodology will be illustrated on various test approaches.

Speed clustering of integrated circuits

Experimental data on 0.18 /spl mu/ test chips shows strong evidence of clustering of speeds of neighboring dies on a wafer. This clustering phenomenon is utilized to develop techniques for predicting the speed of a part from the speeds of three or more of its neighbors. On-chip processor monitors are used to further improve the prediction accuracy of these techniques. Experimental data demonstrates both the effectiveness of these prediction schemes and the possibility of applying of them to reduce the cost of speed binning.

Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits

This paper will propose an overall portfolio of different modern test techniques, like reduced pin-count test, SoC multi-site test, low channel cost ATE, test vector compression, bandwidth matching, and advanced probing technologies, to lower the cost of test. The overall economic benefits, the potential synergies, the overall tradeoffs, and the scalability of the benefits of these techniques, are complex to understand and currently not well understood. This problem will be analyzed in this paper by using technical cost modeling. The dependency of the benefits on different applications will be analyzed by modeling the test cost for four different applications. It will be shown that the right match between the application and a combination of the described techniques can result in a significant reduction of the cost of test. Moreover, it will be shown that this optimal match evolves during technology progress and can enable a scalable reduction of the cost of test.

Test chip experiments at stanford CRC

The idea of the test chip experiments started in ITC 1991 [McCluskey 00]. We wanted to get actual tester data that would answer some questions about manufacturing test of digital ICs. The objective was to find out the relative effectiveness of different test techniques, such as stuck fault tests, delay tests, IDDq, etc.