Ajay Taparia
Maxim Integrated
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Publication
Featured researches published by Ajay Taparia.
IEEE Transactions on Very Large Scale Integration Systems | 2011
Ajay Taparia; Bhaskar Banerjee; Thayamkulangara R. Viswanathan
Power-supply noise is a significant problem in mixed-signal systems on a chip. This is due to the impulse like current drawn by digital CMOS gates which couples to the sensitive analog circuits through supplies and the substrate. A noise-localization technique using on-chip active inductors is proposed. This would make the noise current generated by the digital gates to remain local in the region of the digital gates. This active inductor is designed to have minimum overhead in terms of voltage headroom and area. Simulations of benchmark digital gates, frequency dividers, and buffers demonstrate about 30-dB reduction of noise with this technique. Measured results from a test-chip carrying this design further demonstrate the functionality of this inductor.
IEEE Transactions on Very Large Scale Integration Systems | 2011
Ajay Taparia; Bhaskar Banerjee; Thayamkulangara R. Viswanathan
Managing the switching-noise in mixed-signal systems fabricated on a single chip is becoming increasingly challenging. This needs substantial overheads in both area and power. Existing logic families that minimize switching-noise generation, such as current-steering logic (CSL), current-balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. We present a new logic family called the current-steering CMOS (CS-CMOS) obtained by a simple modification keeping the core CMOS structure in tact to preserve its most attractive features. This family not only reduces the switching noise by a factor of ten but also delivers five times higher speed than CSL and CBL for the same power consumption. Experimental results comparing 15-stage ring-oscillators configured in the CSL and CS-CMOS families and fabricated in a 0.18 μm process show that their energy-delay-products are 6.5 fJ*ns and 1.52 fJ*ns respectively. The usefulness of this new logic family is further demonstrated by synthesizing a cell library of CS-CMOS gates and by using it to simulate benchmark circuits, a decimation filter and a frequency divider.
Archive | 2012
Ozan E. Erdogan; Guozhong Shen; Rajesh Anantharaman; Ajay Taparia; Behrooz Javid; Syed T. Mahmud; Rahim Chowdhury
Archive | 2012
Ozan E. Erdogan; Guozhong Shen; Rajesh Anantharaman; Ajay Taparia; Behrooz Javid; Syed T. Mahmud
Archive | 2012
Ozan E. Erdogan; Guozhong Shen; Rajesh Anantharaman; Ajay Taparia; Behrooz Javid; Syed T. Mahmud
Archive | 2012
Ozan E. Erdogan; Guozhong Shen; Rajesh Anantharaman; Ajay Taparia; Behrooz Javid; Syed T. Mahmud
Archive | 2016
Guozhong Shen; Ozan E. Erdogan; Ajay Taparia; Erik Jonathon Thompson
Archive | 2013
Guozhong Shen; Ozan E. Erdogan; Rajesh Anantharaman; Behrooz Javid; Rahim Chowdhury; Ajay Taparia; Syed T. Mahmud
Archive | 2012
Ozan E. Erdogan; Guozhong Shen; Rajesh Anantharaman; Ajay Taparia; Behrooz Javid; Syed T. Mahmud; Rahim Chowdhury
Archive | 2012
Guozhong Shen; Ozan E. Erdogan; Rajesh Anantharaman; Behrooz Javid; Rahim Chowdhury; Ajay Taparia; Syed T. Mahmud