Thayamkulangara R. Viswanathan

A non-uniform sampling technique for A/D conversion

A signal acquisition technique that will provide a favorable tradeoff between speed and resolution is described. This technique is based on recording the time instants at which the input signal crosses any of the fixed quantization levels and extracting additional information from the nonuniform sample sequence by means of digital signal processing methods. The proposed concepts are verified using both software simulation and board level hardware implementation. The proposed scheme offers significant benefits in the VLSI implementation, mainly in terms of reduced power consumption and smaller chip area.<<ETX>>

A new signal acquisition technique

A signal acquisition technique that will result in a high-resolution high-speed analog-to-digital converter architecture is described. The basic idea is to have a simple analog circuit to acquire information about the input signal at high speed and a more complex digital signal processing block to generate a high-resolution digital output. This technique is based on recording the time instants at which the input signal crosses any of a fixed set of quantization levels and extracting additional information from the nonuniform sample sequence using interpolation methods. A board-level design was implemented to verify these principles for real input signals.<<ETX>>

A highly linear CMOS current-controlled oscillator using a novel frequency detector

A CMOS current-controlled oscillator capable of operating over a range of frequencies (100 MHz to 1.0 GHz) is presented. It achieves a highly linear frequency-variation with control current by using a novel switched-capacitor frequency- detector and a simple single-ended ring oscillator in a feedback loop. The simple low-power circuit does not use operational amplifiers or resistors. This circuit, realized in TSMC 0.18-mum CMOS process shows 0.1% linearity over a tuning range of 100 MHz to 1.0 GHz. The simulated results show power dissipation of 1.7 mW at 1.0 GHz and 326 muW at 100 MHz from a 1.8 V supply.

Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems

Power-supply noise is a significant problem in mixed-signal systems on a chip. This is due to the impulse like current drawn by digital CMOS gates which couples to the sensitive analog circuits through supplies and the substrate. A noise-localization technique using on-chip active inductors is proposed. This would make the noise current generated by the digital gates to remain local in the region of the digital gates. This active inductor is designed to have minimum overhead in terms of voltage headroom and area. Simulations of benchmark digital gates, frequency dividers, and buffers demonstrate about 30-dB reduction of noise with this technique. Measured results from a test-chip carrying this design further demonstrate the functionality of this inductor.

Active inductor for power-supply decoupling in mixed signal systems

A CMOS active inductor circuit intended for power-supply decoupling application is presented. The idea is to minimize the switching noise generated by the digital part of a mixed-signal integrated circuit. This is essential when sensitive analog circuits share the same power supply bus with a digital signal processor. In systems with a single clock, the frequency components of the switching noise are the clock frequency and its harmonics. As clock frequencies exceed 1 GHz, the circuit for filtering the switching noise needs only a modest amount of chip area and thus it can be integrated. Simulation results of the proposed circuit using GSMC 0.18 micron CMOS models are used to arrive at the basis for the design of a decoupling scheme.

CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs

Managing the switching-noise in mixed-signal systems fabricated on a single chip is becoming increasingly challenging. This needs substantial overheads in both area and power. Existing logic families that minimize switching-noise generation, such as current-steering logic (CSL), current-balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. We present a new logic family called the current-steering CMOS (CS-CMOS) obtained by a simple modification keeping the core CMOS structure in tact to preserve its most attractive features. This family not only reduces the switching noise by a factor of ten but also delivers five times higher speed than CSL and CBL for the same power consumption. Experimental results comparing 15-stage ring-oscillators configured in the CSL and CS-CMOS families and fabricated in a 0.18 μm process show that their energy-delay-products are 6.5 fJ*ns and 1.52 fJ*ns respectively. The usefulness of this new logic family is further demonstrated by synthesizing a cell library of CS-CMOS gates and by using it to simulate benchmark circuits, a decimation filter and a frequency divider.

Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems

Low-power CMOS logic circuits operated from a fixed supply voltage can result in uncontrolled conduction over process and temperature variation. Large current-pulses flowing during the logic transitions also cause power-supply noise. Current steered logic known as CSL can mitigate these problems. Here, a fixed bias-current is steered between two distinct paths during the transition between logic states. Constant supply-current eliminates switching noise on the power supply line. The current-biased circuit presented here operates like a normal CMOS gate preserving many of its desirable properties. The key modification is that the output static-voltage of the gate is used to steer the bias current between two paths. During the transition the bias current is used for pulling-up the output node. During the pull-down phase a small local capacitance is charged to provide the current pulse needed for pull-up. The current source resistance in conjunction with the local decoupling capacitor acts as a bypass for the impulse current needed for quick pull-up. This new circuit operates over a wide range of bias currents and, the corresponding speeds vary proportionately. These current-steered CMOS gates (CS- CMOS) are specially targeted for use in low-power, wide dynamic range mixed-signal applications where supply noise must be minimized. Circuit operation and simulation results are presented.

A digital bandgap reference

A digital bandgap reference that provides a programmable reference voltage output is presented. It uses the same idea as an analog bandgap circuit except that the three operations of differencing, scaling and addition are done in the digital domain after converting the operands, the analog junction-diode voltages, into numbers. Digital signal processing provides both precision and programmability. The computed result is converted back to obtain the analog output voltage. The voltage drop across one of the current-biased diodes is used as reference in performing both the analog to digital and digital to analog conversions. Both of these conversions are done in a short time period to ensure that the reference voltage remains constant. Thus the reference voltage value cancels and becomes immaterial. It also becomes easier to address issues like curvature correction in the digital domain. Simulation results are presented for a nominal digital bandgap reference 1.2V with a variation of <;0.22% over -40 to 125μC.

A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC

In this paper we present the design of a Nyquist rate VCO based ADC implemented in 65nm CMOS process. The design achieves a peak SNDR of 63.7dB and a SFDR of 76dB in 10MHz bandwidth while consuming 1.1mW of power and occupying only 0.07mm2 of active area. The pseudo-differential VCO implemented in the prototype achieves better than 9-bits linearity with the overall ADC linearity better than 12 bits. The figure of merit (FoM) is 44fJ/conversion and should improve when implemented in more advanced processes.

Operational current to frequency converter

Voltage or current-controlled oscillators with linear tuning characteristics are needed for Analog to Digital Conversion (ADC). The constant of proportionality between its input control-variable (voltage or current) and output frequency is called conversion-gain. We describe an operational current-to-frequency converter that has a large open-loop conversion-gain like in an operational transconductance element in which the input and output variables are dissimilar. The difference between a current-controlled oscillator and current to frequency converter is that the transfer characteristic of the latter passes through the origin. Such a building block is meant for use in negative feedback circuit-configurations. Here the feedback network dominates the closed-loop transfer characteristics. The ability of such a technique to trade gain for improving linearity and reducing process, voltage and temperature variations, is well known. The idea here is to provide a building block to configure ADCs with different resolutions over a wide range of sampling rates below 1 GHz. We present the architecture of such a device and its achievable performance via simulations using the models of a typical 65nm process technology.