Gopal Paul

Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic

Binary decision diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based synthesis technique using dual rail static differential cascode voltage switch with pass gate (DCVSPG) logic. The method yields around 22% reduction in number of MUX cells. Simulation result using SPICE on 180 nm technology with 1.5 volts supply shows, on an average, 65% reduction in power consumption for frequency ranging up to 1 GHz compared to the result with static CMOS logic. It is envisaged that the proposed approach is useful in realizing low-power circuits

Design and implementation of packet filter firewall using Binary Decision Diagram

Packet filtering is the one of the major contemporary firewall design techniques. An important design goal is to arrive at the decision at the packet only. Implementation of such packet filter using Binary Decision Diagram (BDD) gives more advantages in terms of memory usage and look up time. In the case of the list-based packet filter firewall where rules are checked one by one for each incoming packet, the time taken to decide on a packet is proportional to the number of rules. The performance is improved with rule promotion but that itself a slow procedure. In this work we present a BDD-based approach which gives much better result in terms of number of comparisons or accesses the rule list make. Results on 1 million packets show that for most-accept packets, on an average, 75% reduction happens in such comparisons when BDD-based approach is used over list-based with promotion approach. For most-reject packets this reduction is nearly 34%.

High Speed Power Efficient CGIC Digital Filters For VLSI Applications

Digital filter structures based on current-conversion generalized immittance converter (CGIC) proposed by Antoniou and Rezk possess excellent sensitivity and stability characteristics. In this paper, the CGIC structures of low pass and high pass are analyzed to determine the clock period to be used with these structures for VLSI applications and are modified to reduce the clock period further to increase the speed keeping the sensitivity and stability of these structures are exactly the same as those of the original structures. The modified filters are also power efficient while maintaining the original speed but increase the latency to some extent. With a supply voltage of 5 volts the modified filters show 33% increase in speed and 68% reduction in dynamic power consumption if supply voltage is scaled down without increasing the original speed

A Fuzzy Logic Approach in Emotion Detection and Recognition and Formulation of an Odor-Based Emotional Fitness Assistive System

This paper aims at a Fuzzy relational approach for similar emotions expressed by different subjects by facial expressions and predefined parameters. Different Facial attributes contribute to a wide variety of emotions under varied circumstances. These same features also vary widely from person to person, introducing uncertainty to the process. Facial features like eye-opening, mouth-opening and length of eye-brow constriction from localized areas from a face are Fuzzified and converted into emotion space by employing relational models. This is dealt with Fuzzy Type-2 logic, which reigns supreme in reducing uncertainty.

Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers

Binary decision diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based approach for the synthesis of dual-rail adiabatic MUX circuits. The method yields around 22% reduction in the number of MUX blocks for several benchmark circuits compared to the conventional approach. Simulation result using SPICE on 180 nm technology shows, on an average, 50% reduction in power consumption for frequency ranging up to 300 MHz compared to implementation with static CMOS MUX circuits. At 600 MHz, power saving is observed to be nearly 35%. It is envisaged that the proposed approach is useful in realizing low-power circuits

Power-delay efficient technology mapping of BDD-based circuits using DCVSPG cells

Efficient technology mapping has become an important vehicle in deep-submicron technologies for improving performance-oriented synthesis. On the other hand, library-based Pass Transistor Logic (PTL) synthesis, like Lean Integration with Pass-Transistors (LEAP) synthesis, has drawn significant attention to the VLSI research community. In this paper, we propose three new library cells based on differential cascode voltage Switch with Pass Gate Logic (DCVSPG). Synthesis using these cells outperforms the existing LEAP-based synthesis for BDD-based (Binary Decision Diagram-Based) circuits. Results on benchmark circuits show that the new cell-based mapping technique yields more than 60% reduction in both power and delay in the synthesized circuits.

On finding the minimum test set of a BDD-based circuit

The Binary Decision Diagram (BDD) is a powerful vehicle for large-scale functional specification and circuit design. In this paper, we consider the open problem of generating in polynomial time, the exact minimum set (T) of test vectors for detecting all single stuck-at faults in such a BDD-based circuit synthesized with multiplexors. It is shown that for a single-output circuit, T = 2k, where k is the minimum number of paths that cover all the arcs of the BDD graph. The value of k, and consequently the test set T, can be readily determined by running the max-flow algorithm on a network derived from the BDD, followed by a simple graph traversal. This procedure not only generates the optimal test set in polynomial time, but also obviates the need of employing an ATPG (Automatic Test Pattern Generator) and a fault simulator. For multi-output circuits, the procedure requires slight enhancement.

A BDD-Based Design of an Area-Power Efficient Asynchronous Adder

Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. On the other hand Binary Decision Diagrams (BDDs) have found significant applications for many years in the design, synthesis, verification, and testing of VLSI circuits. In this paper we have presented the design of a hybrid Domino PTL-CMOS based 2-bit asynchronous adder, the PTL part of which is designed using the principles of BDD. The designed asynchronous adder has been implemented for 32-bit and the simulation results indicate a reduction of 16% in number of transistors, 8% in power and 21% in power-delay-area-product over earlier reported results without any compromise in the delay. The implementation has been done using UMC 180nm, 1.5V technology.

A BDD-based approach to design power-aware on-line detectors for digital circuits

The work in this paper is mainly concerned with the development of an algorithm for designing a power-aware on-line detector (OLD), which is used in digital circuits to check faults concurrently. We have used Binary Decision Diagram (BDD) in our methodology on top of the existing work to reduce the dynamic power of an OLD significantly. Experiments on ISCAS89 benchmark circuits have shown, on an average, 41% reduction in dynamic power compared to the existing technique. This reduction can further be made to 57% with marginal impact on area overhead.

A Novel Technology Mapping Technique for BDD-Based Circuits Using LEAP Cells

Library-based Pass Transistor Logic (PTL) synthesis, like Lean Integration with Pass-Transistors (LEAP) synthesis, has drawn significant attention to the VLSI research community. In this paper, we first propose a modified Y3 LEAP cell that was originally invented by K. Yano, Y. Sasaki, K. Rikino and K. Seki [1]. Secondly we propose a new technology dependent mapping technique and compare the results with the existing methods published in [2] and [11]. Our technique yields a significant reduction in number of cells used in the core logic block and in other parameters like power, delay and power-delay-product.