Akichika Shiomi

Hardware implementation of a real-time operating system

This paper proposes a new approach to realize a very high performance real-time OS using VLSI technology. In this method, quick and steady response can be guaranteed by implementing basic operations of a real-time OS as a peripheral chip (Silicon TRON) to be connected to general purpose microprocessors. In order to confirm the effectiveness of this method, most basic system calls of /spl mu/ITRON have been designed using an HDL. Synthesis results using a 0.8 /spl mu/m CMOS technology show that most important part of the system calls can be realized as a VLSI chip. According to the evaluation results based on an FPGA implementation, hardware portion of these functionalities can be executed within 250 ns and the task scheduling can be performed within 750 ns simultaneously, which are about 6 to 50 times faster than software implementation. Accordingly, very high performance real-time systems can be realized by the proposed method.

A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts

This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (application specific integrated processor). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the HW cost (gate count) of the designed pipelined ASIP is minimized under given execution cycle and power consumption constraints. A branch-and-bound algorithm with proposed lower bound functions is used to solve the presented formalization in the PEAS-I system. The experimental results show that the proposed method is found to be effective and efficient.

KJ editor: a card-handling tool for creative work support

KJ method, which was developed for creative thinking, uses cards for making a conceptual map from brainstorming. A card-handling editor for supporting the method is presented and was used for analysing requirements of software. The most important effect of using the editor is that not only the relations between the brainstormed matters but also what is lacking in them can be found. The editor is found to be a very useful tool for recording the creative thinking process, and can be used afterwards for interpreting the specification which is a result of the requirement analysis.

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

In this paper, the effectiveness of the ASIP (Application Specific Instruction set Processor) design system PEAS-III is evaluated through experiments. Examples in experiments are a MIPS R3000 compatible processor, DLX, a simple RISC controller, and PEAS-I core. While they are simple in-order pipelined processors, they have enough facilities for real embedded system design. Through experiments, easiness of design and modification for improvement and design quality in terms of performance and hardware cost are discussed. It has been confirmed that the design method used in PEAS-III is effective to design space exploration for simple pipelined processors.

A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs

This paper introduces a new HW/SW partitioning algorithm for automatic synthesis of a pipelined CPU architecture with multiple identical functional units (MIFUs) of each type in designing ASIPs (Application Specific Integrated Processors). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the performance of the designed ASIP is maximized under given gate count and power consumption constraints, regarding the optimal selection of needed FUs of each type. A branch-and-bound algorithm with proposed lower bound function is used to solve the formalized problem. The experimental results show that the proposed algorithm is found to be effective and efficient.

A hardware/software partitioning algorithm for pipelined instruction set processor

This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this paper is to find a set of HW implemented operations to achieve the highest performance of a pipelined ASIP under a given gate count and power consumption constraint. The method enables to estimate the performance and pipeline hazards of the designed ASIP very accurately. The experimental results show that the proposed method is effective and quite efficient.

Requirement analysis by the KJ editor

The KJ method, a technique for obtaining a panoramic view of entire index card arrangements on a computer display, is described. The KJ editor simulates the activity of arranging index cards on a desk. Such activity is essential for carrying out the so-called KJ method, which is used in Japanese business. The editor is used for requirements analysis. It is found that the editor can be used for recording the analytical thinking process and that the resultant chart becomes a very good medium communication between the design and the sponsor/user.<<ETX>>

VLSI implementation of a real-time operating system

This paper proposes a new approach to realize a very high performance real-time OS using VLSI technology. In order to confirm the effectiveness of this method, the most basic system calls have been designed. According to the evaluation results based on a gate array implementation, hardware portion of system calls can be executed within 4 clocks and the task scheduler can be performed in only 8 clocks simultaneously, which are about 130 to 1880 times faster than software implementation.

VLSI implementation and evaluation of a real‐time operating system

This paper proposed a new approach to create a very high performance real-time operating system (OS) using VLSI technology. In this method, a quick and steady response can be guaranteed by implementing basic operations of a real-time OS as a peripheral chip (Silicon TRON) to be connected to general purpose microprocessors. To confirm the effectiveness of this method, most basic system calls of μITRON have been designed using an HDL. Synthesis results using a 0.8 μm CMOS technology show that the most important part of the system calls can be realized as a VLSI chip. According to the evaluation results based on an FPGA implementation, the hardware portion of these functionalities can be executed within 250 ns and task scheduling can be performed with 750 ns simultaneously, both of which are approximately 6 to 50 times faster than software implementation. Accordingly, very high performance real-time systems can be created by the proposed method.

A hardware/software codesign method for pipelined instruction set processor using adaptive database

Proposes a new method to design an optimal pipelined instruction set processor using a formal HW/SW codesign methodology. First, a HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced briefly. Then, an adaptive database approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in HW/SW partitioning. The experimental results show that the proposed methods are effective and efficient.