Nobuyuki Hikichi

An ASIP instruction set optimization algorithm with functional module sharing constraint

This paper describes a formal method that selects the instruction set of an ASIP (application specific integrated processor) that maximizes the chip performance under the constraints of chip area and power consumption. Our contribution includes a new formalization and algorithm that considers the functional module sharing in the problem of instruction set optimization. This problem was not addressed in the previous work and considering it leads to an efficient implementation of the selected instructions. The proposed method also enables designers to predict the performance of their designs before implementing them, which is an important feature for producing a high quality design in reasonable time.

A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts

This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (application specific integrated processor). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the HW cost (gate count) of the designed pipelined ASIP is minimized under given execution cycle and power consumption constraints. A branch-and-bound algorithm with proposed lower bound functions is used to solve the presented formalization in the PEAS-I system. The experimental results show that the proposed method is found to be effective and efficient.

An integrated design environment for application specific integrated processor

A novel framework for ASIP (application specific integrated processor) development is proposed. The system accepts a set of example programs written in the C language and their expected data as input, and profiles these programs both statically and dynamically. Then taking advantage of the profiled results, the system decides the instruction set and hardware architectures of ASIP, and synthesizes the CPU core design of the ASIP, as well as the software development tools for the ASIP such as compiler and simulator.<<ETX>>

PEAS-I: A hardware/software co-design system for ASIPs

The current implementation and experimental results of the PEAS-1 (practical environment for application specific integrated processor (ASIP) development - Version I) system are described. The PEAS-I system is a hardware/software co-design system for ASIP development. The input to the system is a set of application programs written in C language, an associated data set, and design constraints such as chip area and power consumption. The system generates an optimized CPU core design in the form of an HDL, as well as a set of application program development tools, such as a C compiler, assembler, and simulator. A novel method that formulates the design of an optimal instruction set using an integer programming approach is described. A tool that enables the designer to predict the chip area and performance of the design before the detailed design is completed is discussed. Application program development tools are generated in addition to the ASIP hardware design.<<ETX>>

An integer programming approach to instruction implementation method selection problem

A new algorithm for instruction implementation method selection problem (IMSP) in application specific integrated processors (ASIP) design automation is proposed. This problem is to be solved in the instruction set architecture and CPU core architecture designs. First, the IMSP is formalized as an integer programming problem, which is to maximize the performance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. This algorithm will automate the complex parts of the ASIP chip design.<<ETX>>

A hardware/software partitioning algorithm for pipelined instruction set processor

This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this paper is to find a set of HW implemented operations to achieve the highest performance of a pipelined ASIP under a given gate count and power consumption constraint. The method enables to estimate the performance and pipeline hazards of the designed ASIP very accurately. The experimental results show that the proposed method is effective and quite efficient.

Compiler generation techniques for embedded processors and their application to HW/SW codesign

Due to the advancing semiconductor technology it is becoming possible within ten years to fabricate a highly complex and high performance VLSI that includes more than hundred million transistors on a single silicon chip [1]. Using such a technology, so-called systems-on-a-chip, that includes CPU cores, DSPs, memory blocks (RAM and ROM), application specific hardware modules, FPGA blocks, as well as analog and radio frequency blocks, as shown Figure 1. Systems-on-a-chip will be suitable for embedded applications, such as consumer electronics products that perform sophisticated data and information processing, telecommunication equipment that perform movie picture and audio transmission, control systems for industrial manufacturing, automobile, and avionics.

A hardware/software codesign method for pipelined instruction set processor using adaptive database

Proposes a new method to design an optimal pipelined instruction set processor using a formal HW/SW codesign methodology. First, a HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced briefly. Then, an adaptive database approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in HW/SW partitioning. The experimental results show that the proposed methods are effective and efficient.