Akihiro Chiyonobu

Multiple Clustered Core Processors

This paper proposes multiple clustered core processors as a solution that attains both low power consumption and easy programming facility. Considering the current trend of increasing power consumption and temperature, a lot of CPU venders have shipped or announced to ship multiple core processors. Especially, recent studies on heterogeneous multiple core processors show that they are more efficient in energy utilization than homogeneous ones. However, they request programmers to consider complex task scheduling since the size of every task always has to match the performance of core where it is allocated. Multiple clustered core processors relieve them from such a tedious job. Simulation results show that a multiple clustered core processor consumes slightly more power than a heterogeneous multiple core processor. However, in a case, the heterogeneous multiple core processor cannot solve a severe task scheduling problem, while the multiple clustered core processor can.

Challenges in Evaluations for a Typical-Case Design Methodology

According to the current trend of increasing variations in process technologies and thus in performance, the conservative worst-case design will not work since design margins can not be provided. The authors are investigating a typical-case design methodology, where designers focus on typical cases rather than on rarely-occurring worst cases. On evaluating the typical-case design, accurate circuit delay has to be considered, which is ignored in the current architectural-level simulations. While gate-level simulations consider circuit delay, they require huge amount of simulation time and hence are inappropriate for system designs, where designers examine a wide variety of design choices. In this paper, the authors show the challenges in evaluating designs that are based on the typical-case design methodology, and build a prototype architectural-level simulator, which can estimate circuit delay within tolerable simulation time

Energy-efficient instruction scheduling utilizing cache miss information

Current microprocessors require both high performance and low-power consumption. In order to reduce energy consumption with maintaining computing performance, we propose to utilize the information regarding instruction criticality. Microprocessors we are proposing have two types of functional units distinguished in terms of their execution latency and power consumption. Only critical instructions are executed on power-hungry functional units, and thus the total energy consumption can be reduced without severe performance loss. In order to achieve large energy reduction, it is required to execute instructions on power-efficient units as frequently as possible. In this paper, we propose a new instruction scheduling method utilizing cache miss information over the above mentioned scheduling technique. As a performance gap between microprocessors and main memories is increasing, it is possible that critical instructions are executed in power-efficient units as well as non-critical ones while main memory access is occurring. Our simulation results reveal that the modified instruction scheduling achieves 27.3% ED2P reduction with 1.4% performance degradation.

Power and performance fitting in nanometer design

Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Device engineers, circuit designers, and system architects are faced with many challenges. In the area of mobile and embedded computer platforms, power has already been a major design constraint. However, it is also a limiting factor in general-purpose microprocessors. In order to manage the impact of increasing microprocessor power consumption, architectural-level techniques are required as well as circuit-level design improvements. This paper proposes criticality-based instruction scheduling and Contrail processor architecture, which utilize the criticality of instructions, and demonstrates their effectiveness.

Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors

Soft error tolerance is a hot research topic for modern microprocessors. We have been investigating soft error tolerance micro architecture, RED, which exploits time redundancy to achieve soft error tolerance without requiring prohibitive additional hardware resources. Unfortunately, our previous study unveiled that a RED-based processor suffers severe performance penalty. We guess that it comes from the reduction in effective instruction issue queue (ISQ) capacity. Since RED uses a register update unit (RUU), which combines an ISQ and a reorder buffer (ROB) into a single structure, redundant instructions occupy the ISQ. Actually, contemporary microprocessors use a dedicated ISQ, which is decoupled from the ROB rather than the RUU. In this paper, in order to reduce the performance penalty, we adopt RED into ROB-based microprocessors. We reduce the penalty from 17.4% to 12.4% and from 23.9% to 18.3% for integer and floating-point programs, respectively

Correlation-based critical path predictors for low power microprocessors

Recent studies show that the speed of microprocessors can be accelerated if we can identify which instructions are critical. Exploiting information regarding instruction criticality is effective not only for improving processor performance but also for improving energy efficiency. In this paper, we propose three critical path predictors in order to identify critical instructions. Experimental results demonstrate the future research direction of our approach.

Evaluating the Impact of Fault Recovery on Superscalar Processor Performance

Current semiconductor technologies have become susceptible to high-energy neutrons from space. Following the trends in smaller transistors, lower supply voltage, and higher clock frequency, current microprocessors are susceptible to soft errors, which constitute the vast majority of hardware failures. Based on these trends, it is expected that the quality with respect to reliability becomes important as well as performance for microprocessors. In light of this, a lot of fault-tolerance microarchitectures are recently proposed. These studies mainly focus on detecting transient faults, and hence almost every previous study evaluated processor performance in the absence of faults. This analysis only presents the performance impact of constraints introduced by fault detection mechanism. One of the reasons why this evaluation methodology is widely selected is that faults are expected to be rare enough that the overall performance is determined by fault-free behavior. However, evaluating recovery cost of fault tolerant execution is also important, because it is predicted that transient hardware faults occur more frequently as semiconductor technology is improved. Therefore, this paper focuses on recovery from faults

A Low-Power Instruction Issue Queue for Microprocessors

Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.

Indirect Tag Search Mechanism for Instruction Window Energy Reduction

Instruction window is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction window size should be increased. However, it is difficult to increase the size, since instruction window is implemented by CAM whose power and delay are much large. This paper introduces a low power and scalable instruction window that replaces CAM with RAM. In this window, instructions are explicitly woken up. Evaluation results show that the proposed instruction window decreases performance by only 1.9% on average. Furthermore, dynamic energy is reduced by 67% on average and static power is reduced by 14%.

Improving energy efficiency via speculative multithreading on multicore processors

The advance in semiconductor technologies has increased the number of transistors on a die, resulting in the continuous improvement in microprocessor performance. However, the increase in power consumption and hence in power density is about to stop the progress in microprocessor performance. While supply voltage reduction is commonly known as an effective technique for power savings, it increases gate delay and thus causes performance degradation. The increasing transistors can be utilized for maintaining performance while reducing power consumption. We are considering a speculative multithreaded execution on MultiCore processors. We propose to execute only the part of the program, which has the impact on program execution time, on power-hungry cores. In order to enable this, we divide the instruction stream into two streams. One is called speculation stream, which is the main part of a program and where speculation is applied. It is executed on power-hungry cores. The other is the verification stream, which verifies every speculation. It is executed on low-power cores. The energy consumption is reduced by the decrease in the execution time in the speculation stream and by the low-power execution in the verification stream. We call this technique Contrail architecture. The paper will present the energy efficiency of a Contrail processor based on detailed simulations.