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Proc. of 13th Workshop on Synthesis and System Integration of Mixed Information Technologies | 2006

Multiple Clustered Core Processors

Toshinori Sato; 寿倫 佐藤; Akihiro Chiyonobu; 昭宏 千代延

This paper proposes multiple clustered core processors as a solution that attains both low power consumption and easy programming facility. Considering the current trend of increasing power consumption and temperature, a lot of CPU venders have shipped or announced to ship multiple core processors. Especially, recent studies on heterogeneous multiple core processors show that they are more efficient in energy utilization than homogeneous ones. However, they request programmers to consider complex task scheduling since the size of every task always has to match the performance of core where it is allocated. Multiple clustered core processors relieve them from such a tedious job. Simulation results show that a multiple clustered core processor consumes slightly more power than a heterogeneous multiple core processor. However, in a case, the heterogeneous multiple core processor cannot solve a severe task scheduling problem, while the multiple clustered core processor can.


applied reconfigurable computing | 2006

Evaluating the Critical Path Predictors Using Critical Path Detection Criteria

昭宏 千代延; Akihiro Chiyonobu; 寿倫 佐藤; Toshinori Sato


SLRC Papers Database | 2006

A Preliminary Evaluation of Timing-Speculative Instruction Collapsing

Toshinori Sato; 寿倫 佐藤; Akihiro Chiyonobu; 昭宏 千代延


Distributed Computing | 2006

Utilizing Data Compression to Improve Cache Performance in Multicore Processors with Dedicated Caches

義崇 伊藤; Yoshitaka Ito; 昭宏 千代延; Akihiro Chiyonobu; 寿倫 佐藤; Toshinori Sato


情報処理学会論文誌 | 2007

Low Power Cache Memories Prioritizing Data

昭宏 千代延; Akihiro Chiyonobu; 誠一郎 藤井; Seiichiro Fujii; 寿倫 佐藤; Toshinori Sato


applied reconfigurable computing | 2007

Evaluating Value Predictors in an Energy-Efficent MultiCore Processor

敏正 舟木; 昭宏 千代延; 寿倫 佐藤; Toshimasa Funaki; Akihiro Chiyonobu; Toshinori Sato


Distributed Computing | 2007

A Typical-case Design Methodology Mitigating Timing Constraints and its Evaluation via Co-Simulations

勇次 国武; Yuji Kunitake; 昭宏 千代延; Akihiro Chiyonobu; 康一郎 田中; Koichiro Tanaka; 寿倫 佐藤; Toshinori Sato


Distributed Computing | 2007

タイミング制約違反を利用する設計手法とコ・シミュレーション環境による評価(回路・設計手法)

勇次 国武; 昭宏 千代延; 康一郎 田中; 寿倫 佐藤


5th Symposium on Advanced Computing Systems and Infrastructures, SACSIS 2007 || || p152-153 | 2007

Impact of Wire-delay on On-chip Cache Hierarchies in MultiCore Processors

義崇 伊藤; Yoshitaka Ito; 昭宏 千代延; Akihiro Chiyonobu; 寿倫 佐藤; Toshinori Sato


電子情報通信学会技術研究報告. ICD, 集積回路 | 2006

温度を考慮するアーキテクチャの検討のための物理レジスタアクセス頻度の特徴調査(集積回路技術とアーキテクチャ技術の協調・融合へ向けた,プロセッサ,並列処理,システムLSIアーキテクチャ及び一般)

寿倫 佐藤; 勇次 国武; 昭宏 千代延

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Akihiro Chiyonobu

Kyushu Institute of Technology

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勇次 国武

Kyushu Institute of Technology

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康一郎 田中

Kyushu Institute of Technology

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Koichiro Tanaka

Kyushu Institute of Technology

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Toshimasa Funaki

Kyushu Institute of Technology

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Yoshitaka Ito

Kyushu Institute of Technology

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