Yuji Kunitake

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay

Signal probability control for relieving NBTI in SRAM cells

Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the signal probability. This is because, it is the key parameter of NBTI degradation. Based on the observations, we propose a novel cell-flipping technique in order to make signal probability close to 50%. The long cell-flipping period leads to threshold voltage degradation as large as the original case where the cell-flipping technique is not applied. Thus, we employ the short flipping period to the cell-flipping technique without any stall of operations. In consequence of applying the cell-flipping technique to a register file, we can relieve threshold voltage degradation by 70% after the SRAM cell is used for 3 years.

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications

This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nanojoule while conventional DVS processors need hundreds of microseconds and dissipate a few microjoule for the performance transition (Shin et al., Oct. 2005) (Allah et al., April 2007) .

Possibilities to miss predicting timing errors in canary flip-flops

Deep submicron technologies increase parameter variations, which will make microprocessor designs very difficult, since every variation requires a large safety margin for achieving specified timing yield. This means higher supply voltage, which results in large energy consumption. Razor flip-flop (FF) is a clever technique to eliminate the supply voltage margin by exploiting circuit-level timing speculation. It combines dynamic voltage scaling technique with the error detection and recovery mechanism. We are studying an alternative timing-error-predicting FF, named canary FF. This paper discusses a critical issue regarding the canary FF. Detailed gate- and architectural-level co-simulations unveil that canary FF occasionally misses predicting timing errors.

A case study of Short Term Cell-Flipping technique for mitigating NBTI degradation on cache

Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage shift in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage shifts in the load transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. Because an SRAM cell consists of two inverters, one of the load transistors is always stressed. In order to mitigate NBTI degradation, we proposed Short Term Cell-Flipping technique (STCF) for SRAM cell. This technique makes the stress probability on load transistors in an SRAM cell close to 50%. In this paper, we apply STCF technique to cache memories, and discuss its potential to mitigate NBTI degradation.

A Replacement Strategy for Canary Flip-Flops

The deep sub micron semiconductor technologies increase parameter variations. The increase in parameter variations requires excessive design margin that has serious impact on performance and power consumption. In order to eliminate the excessive design margin, we are investigating canary Flip-Flop (FF). Canary FF requires additional circuits consisting of an FF and a comparator. Thus, it suffers large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method for canary FF and evaluates it. In the case of Renesas’s M32R processor, the area overhead of 2% is achieved.

Challenges in Evaluations for a Typical-Case Design Methodology

According to the current trend of increasing variations in process technologies and thus in performance, the conservative worst-case design will not work since design margins can not be provided. The authors are investigating a typical-case design methodology, where designers focus on typical cases rather than on rarely-occurring worst cases. On evaluating the typical-case design, accurate circuit delay has to be considered, which is ignored in the current architectural-level simulations. While gate-level simulations consider circuit delay, they require huge amount of simulation time and hence are inappropriate for system designs, where designers examine a wide variety of design choices. In this paper, the authors show the challenges in evaluating designs that are based on the typical-case design methodology, and build a prototype architectural-level simulator, which can estimate circuit delay within tolerable simulation time

Exploiting input variations for energy reduction

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. They enable to eliminate design margins as well as to tolerate parameter variations. We are investigating canary logic, which we proposed as a promising technique that enables the typical-case design. Currently, we utilize the canary logic for power reduction by exploiting input variations, and its potential of 30% power reduction in adders has been estimated at gate-level simulations. In this paper, we evaluate how canary logic is effective for power reduction of the entire microprocessor and find 9% energy reduction.

A Selective replacement method for timing-error-predicting flip-flops

The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshibas MeP and Renesas Electronicss M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.

A selective replacement method for timing-error-predicting flip-flops

The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshibas MeP and Renesas Electronicss M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.