Akihiro Kajita

Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM

100 nm half-pitch Cu dual-damascene (DD) interconnects with low-k hybrid (PAE(k2.65)/SiOC(k2.5)/SiC(k3.5)) dielectrics have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid-DD structure was fabricated by applying a hard mask process combined with Stacked Mask Process (S-MAP). Well-controlled DD profile of the hybrid structure can provide the advantage of void-less Cu fill, resulting from over-hang reduction of PVD barrier metal. Stress-induced voiding (SiV), which is becoming a more serious problem with down scaling of via-hole dimension was found to be drastically improved as compared with homogeneous-DD structures. Thermal cycle test (TCT) also shows no degradation of the wiring/via-hole properties. Moreover, the result of electromigration (EM) test shows a tight distribution of mean time to failure (MTF). The hybrid-DD structure can extend the PVD Cu filling process to 65 nm-node Cu metallization with excellent reliability.

Low-Temperature Graphene Growth Originating at Crystalline Facets of Catalytic Metal

We explored the characteristic behavior of low-temperature graphene growth on catalytic metal films. The results suggested that graphene growth originates from the crystalline facets with specific angles with respect to the crystalline orientation of the catalytic metals at low temperatures, which is different from the conventional growth models. The G/D ratio of the Raman spectrum of the graphene film was affected by both the number of specific facets and the width of the terrace. Because of this behavior, it is important to prepare the surface conditions with a smaller number of facets and a wider terrace for high-quality graphene growth at low temperatures.

Fabrication and Characterization of Planarized Carbon Nanotube Via Interconnects

We fabricate planarized carbon nanotube (CNT) via interconnects using chemical mechanical polishing (CMP). The selective growth of CNT bundles in via holes and the filling of spin-on-glass into the space among the CNTs are performed, followed by a CMP process. The via resistance is reduced by post-CMP treatment and post-annealing due to the improvement in the top contact formation. The measured CNT via resistance is higher than the CNT bundle resistance estimated from the measured resistance of an individual CNT. This indicates that contact resistance is higher than the CNT resistance in the CNT via interconnect.

Three bits per cell floating gate NAND flash memory technology for 30nm and beyond

Three bits per cell NAND Flash Memory Technology for 30nm and beyond has been successfully developed with floating gate technology. Tight natural Vth distribution, wide program/erase window, and good cell reliability such as program disturb, endurance and data retention are obtained. 8 level Vth distributions are successfully demonstrated.

A High-performance Multi-level NAND Flash Memory with 43nm-node Floating-gate Technology

Multi-level programming is demonstrated with 43 nm-node NAND floating-gate megabit cells for the first time, by thinning an inter-gate dielectric film to less than 13 nm. 43 nm-node cobalt-silicide control-gate and copper bit-line technologies are developed to achieve low resistances of the word lines and bit lines.

Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond

In order to realize highly reliable low-k/Cu interconnects, optimum BEOL structures were developed for 130, 90 and 65 node logic devices respectively. For 65 nm node BEOL structure, the conventional monolithic dual damascene (DD) structure was replaced by the hybrid-DD structure with PAr/SiOC stack films. It shows high extendibility to the next generation using newly developed technologies, such as eBeam cure and damage restoration techniques.

Floating Gate super multi level NAND Flash Memory Technology for 30nm and beyond

A floating gate NAND flash memory technology for 30 nm and beyond has been successfully developed. Wide program/erase window, tight natural threshold voltage (Vth) distribution, and good cell reliabilities such as program disturb, program/erase endurance and data retention are successfully demonstrated, which are essential to realize super MLC.

Bromine doping of multilayer graphene for low-resistance interconnects

Multilayer graphene (MLG) is expected to be a low-resistance and high-reliability interconnect material replacing copper (Cu) in nanoscale interconnects. To achieve low-resistance interconnect with MLG, carrier doping is necessary since the carrier concentrations in pristine MLGs are low. In this work, the effects of bromine (Br) doping by intercalation on the carrier concentration and sheet resistance of exfoliated highly oriented pyrolytic graphite (HOPG) were investigated by measuring the Fermi level shift using ultraviolet photoelectron spectroscopy (UPS) and the four-terminal method, respectively. The Fermi level was shifted downward up to 0.63 eV, and the sheet resistance was reduced to less than 10% of that of the pristine HOPG by increasing the Br concentration. A similar Fermi level shift was observed for the commercially available CVD-MLG. Br doping is thus promising for low-resistance MLG interconnects from the perspective of carrier doping.

Electrical properties of multilayer graphene interconnects prepared by chemical vapor deposition

We fabricate multilayer graphene interconnects with 100-nm-class line widths. Multilayer graphene is grown on a Ni catalyst layer using remote plasma-enhanced chemical vapor deposition (CVD) at a low temperature of 600°C and transferred onto a SiO2/Si substrate after exfoliation from the Ni layer. The sheet resistance of the CVD graphene interconnects is as low as 500 Ω sq. The temperature dependence of resistance reveals that the CVD graphene exhibits half-metallic transport properties.

Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified