Hideki Shibata

Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Copper (Cu) dual-damascene interconnects with a self-formed MnSi xOy barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSixOy layer was formed at the interface of Cu and dielectric SiO2, and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO2, suggesting that MnSixOy layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via

NURA: a feasible, gas-dielectric interconnect process

We have proposed a gas-dielectric interconnect process, and demonstrated its feasibility. While several engineering problems need to tackled before the proposed process is manufacturable, the incentive for further development of this process is huge since it can lead to the minimum physical value of the relative dielectric constant, 1.0.

The Effects of Al(111) Crystal Orientation on Electromigration in Half-Micron Layered Al Interconnects

A study has been done on the crystallographic effects of under-metal planes on Al(111) orientation in layered Al interconnects (Al/Ti, Al/TiN/Ti), and the dominant factor for electromigration was clarified in the region below a half-micron line width. It was found that Al(111) preferred orientation is strongly dependent on the crystal structure and process sequence of the under-metal, and universally determined by the difference between the spacing of Al(111) plane and under-metal planes. Moreover, it was found that the electromigration endurance tends to improve in proportion to the degree of Al(111) preferred orientation. Therefore, the formation of an under-metal layer with an appropriate plane whose spacing is close to that of the Al(111) plane is the most significant criterion for the realization of highly oriented Al(111) planes and hence highly reliable ULSI interconnects.

On-chip optical interconnection by using integrated III-V laser diode and photodetector with silicon waveguide

On-chip integration of III-V laser diodes and photodetectors with silicon nanowire waveguides is demonstrated. Through flip-chip bonding of GaInNAs/GaAs laser diodes directly onto the silicon substrate, efficient heat dissipation was realized and characteristic temperatures as high as 132K were achieved. Spot-size converters for the laser-to-waveguide coupling were used, with efficiencies greater than 60%. The photodetectors were fabricated by bonding of InGaAs/InP wafers directly to silicon waveguides and formation of metal-semiconductor-metal structures, giving responsivities as high as 0.74 A/W. Both laser diode and the photodetector were integrated with a single silicon waveguide to demonstrate a complete on-chip optical transmission link.

Use of gas as low-k interlayer dielectric in LSI's: Demonstration of feasibility

Reduction of the wire capacitance in LSIs has become an issue of the utmost importance since the wire parasitic capacitance plays a significant role in determining both chip speed and power. Low dielectric constant materials such as SiOF (k=3.3) are already in use in manufacturing, while other materials with lower dielectric constants (k=2.0/spl sim/3.0) are under development. Technology for further reduction of the dielectric constant, however, has not been reported so far. In this paper, we propose a gas-dielectric process that has the potential to achieve almost the minimum physically possible value for the dielectric constant: 1.0. The conceptual feasibility of the process is demonstrated, and basic process characterization data are presented. In addition, issues to be considered when integrating the proposed process into LSI manufacturing are identified, and work currently in progress addressing these issues is discussed.

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

We propose an IBA scheme based on a pull-out detection, which is suitable for implementing in a circuit. The scheme is implemented in a driver IC that is part of a module with an RF MEMS variable capacitor. No failures are observed over 108 cycles at 85degC, which is an accelerated charging condition.

High performance half-micron PMOSFETs with 0.1um shallow P + N junction utilizing selective silicon growth and rapid thermal annealing

High performance half-micron PMOSFETs with extremely shallow junction and low parasitic resistance have been realized utilizing selective silicon growth(SSG) with rapid thermal anneal(RTA) processing. In the technology, SSG greatly contributes to reduction of effective junction depth for MOSFETs because of raised source/drain(S/D) structures, and RTA can effectively reduce the junction depth, S/D resistance, and contact resistance due to its excellent activation characteristics of implanted ions and anneal-out of fluorine induced defects. By combining SSG with RTA, shallow P+N junction of 0.1µm depth, sheet resistance of 56ohm/square, and contact resistance of 30ohms for 0.8µm2contact were achieved simultaneously. Moreover, this device structure can provide relaxed alignment tolerances as well as more reliable contact characteristics by avoiding aluminum spiking. The feasibility of the fabrication process and device structure has been demonstrated.

Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed MnSi/sub x/O/sub y/ barrier layer

Copper (Cu) dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier layer using a copper-manganese (Cu-Mn) alloy seed layer is successfully fabricated for the first time. No delamination is found in the chemical mechanical polishing process, probably because of better adhesion strength between the MnSi/sub x/O/sub y/ barrier and dielectric. More than 90% yield is obtained for a 1 million via chain. Microstructure analysis by transmission electron microscopy shows that an approximately 2 nm thick and continuous MnSi/sub x/O/sub y/ layer is formed at the interface between Cu and dielectric of the via and trench and there is no barrier at the via bottom. This via structure without the bottom barrier provides these essential advantages: reduced via resistance; significant via-electromigration lifetime improvement due to there being no flux divergence site at the via; excellent stress-induced voiding performance.

Cost-effective air-gap interconnects by all-in-one post-removing process

Low process cost air-gap structure for multilevel interconnect system is proposed by all-in-one post-removing process. Problems regarding the air-gap process were studied and solutions for moisture uptake and for metal wiring oxidation were developed. The proposed air-gap process is compatible with the conventional BEOL process. Furthermore, this process can build the air-gap structure with least additional process steps, and it tolerates misalignment.

Effect of Plasma Treatment and Dielectric Diffusion Barrier on Electromigration Performance of Copper Damascene Interconnects

The effect of plasma treatment and a dielectric diffusion barrier on electromigration (EM) performance was examined. The characteristics and adhesion properties at the interface between copper (Cu) and the dielectric diffusion barrier were also investigated by scanning transmission electron microscopy–electron energy loss spectrometry (STEM–EELS). The existence of oxygen at the interface after hydrogen (H2) plasma treatment, which has a large pre-exponential factor, causes a large EM drift velocity. Ammonium (NH3) plasma treatment can reduce the Cu oxide completely, resulting in an improvement in EM performance. On the other hand, the dielectric diffusion barrier of SiCxNy, which has a better adhesion property then SiCx, reduces EM drift velocity and provides a larger activation energy. The reduction of CuOx completely by plasma treatment is essential and the selection of dielectric diffusion barrier is important to improve the EM performance of Cu damascene interconnects.