Atsunobu Isobayashi

Low-Temperature Graphene Growth Originating at Crystalline Facets of Catalytic Metal

We explored the characteristic behavior of low-temperature graphene growth on catalytic metal films. The results suggested that graphene growth originates from the crystalline facets with specific angles with respect to the crystalline orientation of the catalytic metals at low temperatures, which is different from the conventional growth models. The G/D ratio of the Raman spectrum of the graphene film was affected by both the number of specific facets and the width of the terrace. Because of this behavior, it is important to prepare the surface conditions with a smaller number of facets and a wider terrace for high-quality graphene growth at low temperatures.

Fabrication and Characterization of Planarized Carbon Nanotube Via Interconnects

We fabricate planarized carbon nanotube (CNT) via interconnects using chemical mechanical polishing (CMP). The selective growth of CNT bundles in via holes and the filling of spin-on-glass into the space among the CNTs are performed, followed by a CMP process. The via resistance is reduced by post-CMP treatment and post-annealing due to the improvement in the top contact formation. The measured CNT via resistance is higher than the CNT bundle resistance estimated from the measured resistance of an individual CNT. This indicates that contact resistance is higher than the CNT resistance in the CNT via interconnect.

Selective carbon nanotube growth in via structure using novel arrangement of catalytic metal

We fabricated a carbon nanotube (CNT) via structure on a 300-mm wafer. We investigated the CNT chemical-mechanical polishing (CNT-CMP) behavior in an actual via pattern structure and clarified the technical issues of the CNT-CMP process. We developed a fabrication process of CNT via structures using selective CNT growth, which has a high potential for applying CNTs to high aspect ratio via structures.

Graphene interconenets selectively grown on catalytic metal damascene structure and its growth mechanism on Ni catalyst

The present work investigated the possibility of the formation of graphene interconnects and studied the behavior of graphene growth in wiring structure. Graphene nucleated on the facet of catalytic metal, and multi layer graphene grew along the terrace surface of catalytic metal. Selective graphene growth served the stacked interconnects structure of graphene / Ni catalytic metal.

A Study on Electrical Resistance of Carbon Nanotubes and Their Metal Contacts Using Simplified Test Structure

In order to realize a high conductive carbon nanotube (CNT) via structure, an accurate evaluation of electrical properties of CNTs and their metal contacts is essential. We succeeded in evaluating the resistance of CNTs and their contacts individually by using our proposed test method and test structure. The contact resistance of CNTs to metals was dependent on the types of contacting metals, which can be explained by the Gibbs energy of oxide formation and differences in work functions of each metal with CNTs and adhesion property. Ti and Pd had common chemical and mechanical characteristics and showed the lowest contact resistance with CNTs among contact metals we used.

Robust and low cost copper contact application for low power device at 32 nm-Node and beyond

We have demonstrated the complete copper filling of contact structures at 32 nm- and 22 nm-node dimensions with the conventional PVD only Ta(N)/Cu barrier/seed process. Copper seed process was optimized to obtain the sufficient coverage of copper along the contact hole with the sufficiently wide gap opening at the top by the use of the directional sputtering and the re-sputtering techniques. In addition, this process was implemented on fully integrated 32 nm-node device wafers and the optimized process produced sufficient performance to meet 32 nm-node requirements. The investigation also included two cases with intentional departure from the optimal conditions, one with a low thickness barrier and the other without copper re-sputtering. In both cases negative influence on front-end-of-the-line (FEOL) parameters was observed.

Electrical properties of 30 nm width bi-layer interconnects of multi layer graphene and Ni

We have fabricated the stacked interconnects of multi-layer graphene (MLG) and nickel (Ni) at the line width from 30 to 1000 nm in 300 mm wafer. MLG, which was grown by CVD process, was selectively deposited on Ni damascene interconnects by the catalytic reaction of Ni. MLG grown from C2H2 was composed of approximately 20 layers of graphene sheets and covered the overall surface of Ni interconnects. Two processes, one with the gas mixture of C2H2/Ar and the other with only Ar gas, were compared and short failure was observed at the comb structure specifically by the usage of C2H2 gas. Along with the failure analysis, this short failure was suggested to be caused by the unintended growth of carbon material from the Ni nanoparticle on the interconnects. An addition of ashing process improved the electrical performance with the minimum damage to MLG. At last, crystalline analysis of MLG suggests a necessity of a continuous process optimization of CVD process for positive influence on resistivity of the interconnects.

Resistance reduction of CNTs on 300-mm wafer by using two precursors with different growth methods

The process conditions for improving the electrical properties of carbon nanotubes (CNTs) were investigated by using a blanket-structure method for quantifying CNT resistance independently. The growth mechanism of CNTs formed with two different gas precursors was investigated from the viewpoint of crystallinity, growth-length uniformity, and resistance. Although the formed CNTs still require further improvements to obtain a ballistic transport property, it was found that the resistance of CNTs is reduced by using a two-step growth method that produces a multi-wall CNT structure and a uniform micrometer-order growth length.

A Monte Carlo simulation of electron transport in Cu nano-interconnects: Suppression of resistance degradation due to LER/LWR

The effect of Line-Edge Roughness (LER) on electrical resistance in nanoscale Cu wires is investigated utilizing a semi-classical Monte Carlo method for simulating electron transport in metallic wires. Dependence of parameters characterizing LER such as amplitude, correlation length, and correlation between line-edges on electrical resistance is presented, and an optimal wire structure to suppress resistance degradation due to LER/LWR is discussed.

Highly Thermo-stable and Oriented Catalytic Metal using Co/Ir/Ta Layer Stack for Graphene Growth

This paper demonstrates that a Co/Ir/Ta stacked layer functions as an excellent catalytic metal structure for low temperature graphene growth. Highly crystalline orientation with no agglomeration for graphene growth at 600°C was achieved even with 10nm Co on Ir/Ta and resulted in the growth of flat multi-layer graphene. Moreover, a trench pattern was utilized to enhance graphene nucleation. Continuous graphene was realized by using Co/Ir/Ta. This shows that it is feasibile to fabricate graphene film with fewer defects. In conclusion, this proposed scheme is a strong candidate of graphene wiring process for LSI interconnects.