Akiko Makihara

Analysis of single-ion multiple-bit upset in high-density DRAMs

New types of multiple-bit upset (MBU) modes have been identified in high density DRAMs (16 Mbit and 64 Mbit). The identification of the mechanisms responsible for the new modes is based on detailed physical bit-map analysis.

Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

We designed logic cells hardened for single-event upsets/single-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKIs 0.15 /spl mu/m fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR . Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/cm/sup 2/).

Single-event effects in 0.18 /spl mu/m CMOS commercial processes

We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.

Optimization for SEU/SET Immunity on 0.15

We designed logic cells hardened for SEUs/SETs using hardness-by-design (HBD) methodology with OKIs 0.15 mum Fully Depleted CMOS/SOI commercial process and these cells were evaluated with sample devices. Our previous work demonstrated that SET-free inverters could be successfully applied as SEU-immune latches. In this work, the logic cells were optimized for SEU/SET immunity up to an LET of 64 MeV/(mg/cm 2), demonstrating that the process was suitable for space applications with a little penalty

\mu

The new SET characterization technique for 0.15 mum Fully Depleted CMOS/SOI digital circuitries was investigated using SPICE and TCAD simulations. The SPICE simulation with a switch can readily reproduce the corresponding SET voltage response for a certain LET. This technique is valid as an alternative in all load and complementary transistor conditions, irrespective of the presence of a plateau region in the SET current waveform generated in a struck transistor.

m Fully Depleted CMOS/SOI Digital Logic Devices

We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.

New SET Characterization Technique Using SPICE for Fully Depleted CMOS/SOI Digital Circuitry

In recent years, due to the demand for increased integration and device scaling, integrated circuits (ICs) have been designed with the design rule less than 100 nm. In these ICs, single-event upsets (SEUs) and single-event transients (SETs) are serious problems because their supply voltage and the threshold voltage of the transistors are decreased. A DICE memory cell is said to have excellent tolerance against SEUs. A DICE-based flip-flop with a SET pulse discriminator circuit on a 90-nm bulk CMOS was designed and fabricated. Its improved performance was demonstrated through radiation testing and discussion was made in comparison with a TMR. SEU sensitivity for the angled irradiation was measured and discussed in this study. The test of edge-on irradiation was performed for the first time. The importance of the angled irradiation for the memory cells that have redundant memory nodes was demonstrated.

SEE in a 0.15 /spl mu/m fully depleted CMOS/SOI commercial Process

Redundant pairs of SOI transistors have been utilized as a Radiation Hardening-By-Design technique. Their applicability was subsequently extended for analog circuits, such as current mirror circuits, and successfully demonstrated with a phase-locked loop circuit.

DICE-Based Flip-Flop With SET Pulse Discriminator on a 90 nm Bulk CMOS Process

This paper describes the Single Event Effect test result on the Radiation Hardness-By-Design SRAM for 0.15µm Fully Depleted CMOS/SOI-ASIC fabricated by a commercial foundry. Sufficient immunity was demonstrated for the SEU/SET required for space applications.

Applicability of Redundant Pairs of SOI Transistors for Analog Circuits and Their Applications to Phase-Locked Loop Circuits

This paper describes Total Ionizing Dose and Single Event Effects test results of a Radiation Hardness-By-Design Library for 0.15μm Fully Depleted CMOS/SOI-ASIC at a commercial foundry. Reasonable data was obtained to improve the library.