S. Kuboyama
Japan Aerospace Exploration Agency
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Featured researches published by S. Kuboyama.
IEEE Transactions on Nuclear Science | 2005
Akiko Makihara; M. Midorikawa; T. Yamaguchi; Yoshiya Iide; T. Yokose; Y. Tsuchiya; T. Arimitsu; Hiroaki Asai; Hiroyuki Shindou; S. Kuboyama; Sumio Matsuda
We designed logic cells hardened for single-event upsets/single-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKIs 0.15 /spl mu/m fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR . Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/cm/sup 2/).
IEEE Transactions on Nuclear Science | 2003
Akiko Makihara; Y. Sakaide; Y. Tsuchiya; T. Arimitsu; Hiroaki Asai; Yoshiya Iide; Hiroyuki Shindou; S. Kuboyama; Sumio Matsuda
We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.
european conference on radiation and its effects on components and systems | 2013
Eiichi Mizuta; S. Kuboyama; Hiroshi Abe; Y. Iwata
It was demonstrated that single-event burnout (SEBs) was observed in silicon carbide power MOSFETs caused by heavy ion and proton irradiations. In addition to SEBs, permanent damage (increase of the drain leakage current) was also observed with higher LET ions similar to SiC Schottky Barrier diodes. For lower LET ions including protons, there were no leakage current increase just before SEBs were observed. The phenomenon is unique for SiC devices.
IEEE Transactions on Nuclear Science | 2006
Akiko Makihara; T. Yamaguchi; Hiroaki Asai; Y. Tsuchiya; Y. Amano; M. Midorikawa; Hiroyuki Shindou; S. Onoda; Toshio Hirao; Y. Nakajima; T. Takahashi; K. Ohnishi; S. Kuboyama
We designed logic cells hardened for SEUs/SETs using hardness-by-design (HBD) methodology with OKIs 0.15 mum Fully Depleted CMOS/SOI commercial process and these cells were evaluated with sample devices. Our previous work demonstrated that SET-free inverters could be successfully applied as SEU-immune latches. In this work, the logic cells were optimized for SEU/SET immunity up to an LET of 64 MeV/(mg/cm 2), demonstrating that the process was suitable for space applications with a little penalty
IEEE Transactions on Nuclear Science | 2003
Hiroyuki Shindou; S. Kuboyama; Naomi Ikeda; Toshio Hirao; Sumio Matsuda
A new failure mode that is attributable to the bulk damage caused by single protons has been reported in 256-Mbit SDRAMs. The refresh rate required to retain memorized data was measured as a typical parameter to detect the effect. We performed the proton irradiation test and discussed results regarding the influence of this failure.
IEEE Transactions on Nuclear Science | 2008
Akiko Makihara; T. Ebihara; T. Yokose; Y. Tsuchiya; Y. Amano; Hiroyuki Shindou; R. Imagawa; Yoshihiro Takahashi; S. Kuboyama
The new SET characterization technique for 0.15 mum Fully Depleted CMOS/SOI digital circuitries was investigated using SPICE and TCAD simulations. The SPICE simulation with a switch can readily reproduce the corresponding SET voltage response for a certain LET. This technique is valid as an alternative in all load and complementary transistor conditions, irrespective of the presence of a plateau region in the SET current waveform generated in a struck transistor.
IEEE Transactions on Nuclear Science | 2004
Akiko Makihara; T. Yamaguchi; Y. Tsuchiya; T. Arimitsu; Hiroaki Asai; Yoshiya Iide; Hiroyuki Shindou; S. Kuboyama; Sumio Matsuda
We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.
IEEE Transactions on Nuclear Science | 2007
Hiroyuki Shindou; S. Kuboyama; Naomi Ikeda; Yohei Satoh; Toshio Hirao; Takashi Tamura
We describe proton induced bulk damage observed in 90 nm process SDRAM. The degradation of the data retention ability was evaluated. The effect due to the difference of process technology and memory cell structure was discussed. The result indicates that the value of the capacitance of the storage capacitor and the volume of the depletion region are key parameters concerning the failures caused by bulk damage.
IEEE Transactions on Nuclear Science | 2005
Hiroyuki Shindou; S. Kuboyama; Toshio Hirao; Sumio Matsuda
The characteristic nondestructive single-event latchup (SEL) phenomena, local and pseudo SELs, were identified in complex digital Large Scale Integrations (LSIs) by using a photo-emission microscope. Usually, SELs are detected as an abrupt increase of power supply current. However, it was experimentally demonstrated that the simple method could not give sufficient information to determine if it is a destructive or a nondestructive phenomenon. If the observed SELs can be confirmed as a nondestructive phenomenon with a certain confidence level, a simple circumvention technique can be effectively employed and the chance to utilize attractive commercial devices will be greatly enhanced. The SEL test method to identify this type of LSI was discussed and a new procedure was proposed.
european conference on radiation and its effects on components and systems | 2011
Akiko Makihara; T. Yokose; Y. Tsuchiya; Yoshio Miyazaki; T. Ebihara; Akifumi Maru; Hiroyuki Shindou; S. Kuboyama
This paper describes the Single Event Effect test result on the Radiation Hardness-By-Design SRAM for 0.15µm Fully Depleted CMOS/SOI-ASIC fabricated by a commercial foundry. Sufficient immunity was demonstrated for the SEU/SET required for space applications.