Akira Akahori

A new optimization procedure for single flux quantum circuits

We have proposed a new optimization procedure for single flux quantum circuits. We have combined Monte-Carlo method with the critical margin method. First, Monte-Carlo method is used to scatter circuit parameters around the initial values. Typically, 50 sets of the circuit parameters are created. Then, the critical margin method is applied in each set. Finally, a circuit that has the largest critical margin among these sets is chosen as an optimized circuit. We fabricated circuits with parameter sets before and after each step optimization circuits and demonstrated that the circuit after the third step optimization was operated with large bias margins at the designed value.

Broad band software-defined radio receivers based on superconductive devices

We have studied software-defined radios (SDRs) based on superconducting devices. The increasing data rate in mobile communications will require a band-width of up to a few hundred MHz in the future. We have confirmed numerically the broad-band characteristic of oversampled analog-to-digital converters including a lowpass and bandpass modulator. Furthermore, the bandpass modulator constructed without a resistor is found to have sensitivity improved by two orders of magnitude compared to that of the lowpass modulator. This result means that the digital RF radio architecture based on a bandpass ADC is better suited for a future SDR receiver.

On-chip test of the shift register for high-end network switch based on cell-based design

We have demonstrated the high-speed operation up to 55 GHz with a bias margin of ±5.5% for a shift register based on the single-flux-quantum logic circuit. The shift register is employed in the rate transfer circuit in high-end network switches that are made up with the cell-based design technique. The on-chip test system was used for measuring the operation frequencies, and the test system itself was built by combining the cells to satisfy the boundary conditions between the test system and the circuit-under-test. As a result, the on-chip test system developed in this study has high flexibility.

Design and demonstration of SFQ pipelined multiplier

We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSAs). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of /spl plusmn/5.5%.

Demonstration of decimation filter and high-speed testing of a component of the filter

We study decimation filters based on the single-flux-quantum circuit in order to realize over-sampled AD converter. We designed the decimation digital filters using CONNECT cells, a well-developed cell library. We designed a T1 cell, because the T1 cell is the key for the counting-type decimation filter. We confirmed correct operation up to 43 GHz by using an on chip test system. Using the T1 cell, we designed second-order counting-type decimation sinc filters with decimation factors N=2 and N=4. The circuit scale was as high as 2758 junctions. We also confirmed the correct operation of these filters.

Pipelined architecture based on single flux quantum with resettable latch

Abstract We have already proposed single flux quantum with resettable latch (SFQ-RL). SFQ-RL was proposed as a new SFQ logic, which consists of “L-gate”, “confluence buffer” and “splitter”. We can realize the pipelined circuits easily using SFQ-RL, because the pipelined circuits are constructed by connecting L-gates in series. We have reported the full operation of the half adder based on SFQ-RL before. As the application of SFQ-RL to the more complicated circuits with a pipelined structure, we have designed pipelined carry save serial adder (CSSA). We have confirmed the partial operation of CSSA.

Demonstration of the SFQ pipelined circuit at 14 GHz

Abstract We have tested a pipelined SFQ circuit at high clock frequencies using the on-chip test system. The circuit under test (CUT) is a half adder (HA), which has the structure of a two-stage pipeline. To simplify the on-chip test system, a two bit-shift register (SR) is added to the HA. This SR has a “Data-Out” terminal and a “Tap-Out” terminal, which are connected to the two “Input” terminals of the HA. This structure reduces the number of the input terminals of the CUT to one terminal and is regarded as one of the basic component of the digital filter. We have confirmed that the CUT operates correctly with wide bias margins up to 14 GHz.

Design and demonstration of fundamental logic circuits based on a single-flux-quantum gate with a resettable latch

We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NECs standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.