Futoshi Furuta

Fabricating 3D integrated CMOS devices by using wafer stacking and via-last TSV technologies

A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings both seamless copper bonding and void-less underfilling in face-to-face (F2F) and back-to-face (B2F) configurations. The backside-via-last TSV processes provide electrical connection between a TSV and copper/low-k interconnects without causing low-k damage. The low capacitance (around 40 fF) of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV (i.e., below 50 MPa at 2 μm from a TSV edge).

High-speed operation of demultiplexer up to 56 GHz

A 1-to-4 demultiplexer (DEMUX) was designed based on Single Flux Quantum (SFQ) circuitry and high-speed operation was confirmed using on-chip testing. The circuit was designed with a binary-tree structure to enable high-speed operation. We also investigated timing between clock and data signals in detail. Monte Carlo simulation was applied to vary the design parameters pseudo-randomly and the spread of timing was obtained by circuit simulation. Even if the circuit parameters varied as a result of the fabrication process, proper timing was maintained by optimizing the length of Josephson transmission line. The 1-to-4 DEMUX we fabricated distributed data signals correctly at operating frequencies up to 56 GHz with a bias margin of /spl plusmn/7%.

Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme

This paper proposes a method to reduce the supply voltage IR drop of 3D stacked-die systems by implementing an on-chip Buck Converter on Top die (BCT) scheme. The IR drop is caused by the parasitic resistance of Through Silicon Vias (TSVs) used in the 3D integration. The IR drop reduction and the overhead associated with the BCT scheme are modeled and analyzed. A 3D stacked-die system is manufactured using 90nm CMOS technology with TSVs and a silicon interposer. A chip inductor and chip capacitors for the buck converter are mounted directly on the top die. The reduction of the IR drop to less than 1/4 is verified through experiments.

A study for an improved design of front-end circuit of Superconducting analog-to-digital converter

We have proposed an improved design of the front-end circuit for superconducting analog-to-digital (A/D) converters. The assumed structure of the A/D converter consists of a front-end circuit based on single flux quantum circuitry and a back-end circuit based on semiconductor circuits. To complete the A/D converter, it is necessary to enable synchronous operation between the front-end circuit and assumed back-end circuit. In the present framework, the front-end circuit consists of a ladder-type pulse generator, a modulator, a hybrid DEMUX, shift-registers and stack-type amplifiers. The voltage level of the output data signal is enlarged to about 10 mV by using stack-type amplifiers. Furthermore, the timing margin for synchronization is improved by using a hybrid demultiplexing method. We also have designed a front-end circuit based on the present framework and verified its functionalities at low speed. It was experimentally confirmed that the timing margin in a 1-to-4 hybrid DEMUX was enlarged to three times as large as in the conventional binary-tree DEMUX. A high-voltage output signal of 11 mV was also obtained. From these results, we conclude that functionalities of the designed front-end circuit are correct.

Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration

Successful 3D integration of a stacked chip fabricated by a “chip-level through-silicon-via (TSV)” process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.

Experimental Evaluation of Signal-to-Noise Ratio of Sigma-Delta Modulator for Superconducting Analog-to-Digital Converter

We designed a superconducting front-end circuit for an analog-to-digital converter and experimentally evaluated its signal-to-noise-ratio (SNR) at a sampling frequency of 10 GHz. The modulator was based on a first-order sigma-delta modulation with an LR integrator. Correct noise shaping was experimentally confirmed, and an SNR of 70.9 dB at a bandwidth of 10 MHz was achieved. In the circuit design, we investigated the effect of leakage in the LR integrator and thermal noise on the SNR by using transfer function analysis and circuit simulations with noise sources. Circuit parameters were designed to keep the discrepancy of the SNR from the ideal value (77.6 dB) within 6 dB. In the experimental evaluation, the modulated data signal from the superconducting chip was accumulated with room-temperature electronics. A fast Fourier transform (FFT) calculation was performed to obtain power spectra and SNRs. The power spectra and SNRs were consistent with the predictions of the transfer function analysis and circuit simulations.

Characteristics of Superconducting First-Order Sigma-Delta Modulator With Clock-Doubler Circuit

Superconducting first-order sigma-delta modulator was designed and evaluated experimentally at the sampling frequency (fs) over 10 GHz using an internal clock-doubler circuit. We employed a complementary-feedback type first-order sigma-delta modulator with an LR integrator. The numerical simulation indicated that higher fs of 20 GHz are required to achieve 14-bit resolution for the signal bandwidth of 10 MHz. We newly developed a frequency doubler circuit to generate 20 GHz clock signals from external 10 GHz signals. The modulator could be evaluated experimentally at fs up to 16 GHz, which limited by the measurement system. The measured SINAD (signal-to-noise-and-distortion ratio) of the modulator is almost equal to the numerically simulated value, and the SINAD at 16 GHz is about 77 dB for the signal bandwidth of 10 MHz.

High-speed operation of front-end circuit of analog-to-digital converter

Abstract We designed a front-end circuit of an analog-to-digital converter based on single flux quantum circuitry and tested its high-speed operation. The front-end circuit consists of a clock oscillator, a sigma–delta modulator, a 1-to-8 demultiplexer (DEMUX) and SQUID amplifiers (SQUID AMP’s). The total number of Josephson junctions is 2518. In the test, a dc current was supplied to the modulator and the output digital data were distributed by the DEMUX and amplified by the SQUID AMP’s. The distributed output data was successfully acquired at high-speed by using an on-chip testing method. To confirm the proper function of the circuit, we studied the dependence of the ratio of the logical value “1” on the current level. As a result, we found that the ratio was proportional to the magnitude of the dc current. At the same time, we also confirmed the amplifications of the SQUID AMP’s. These results indicate that the front-end circuit was operated correctly. The maximum operating frequency of the circuit was 43 GHz.

Investigation of basic properties of an HTS sigma-delta modulator

Abstract We fabricated and tested a high-temperature superconducting sigma–delta modulator using interface-engineered Josephson junctions. Proper dc-characteristics were obtained with a sampling frequency of 100 GHz at 20 K. To achieve high-speed sampling, Josephson junctions with a higher critical-current normal-resistance product were used. Circuit simulations with thermal noise were performed for the analysis of switching characteristics and SFQ dynamics. Further numerical analysis was made for the estimation of signal to noise ratio. Resultant bit accuracy was found to be 10.4 for 122 MHz input signal band.

6 Tbps/W, 1 Tbps/mm 2 , 3D interconnect using adaptive timing control and low capacitance TSV

We describe a Through Silicon Via (TSV) interconnect for multi-layer stacked chips by using a low capacitance TSV and by introducing a novel circuit design with an adaptive timing control. Studying effects of TSV parasitic capacitances on the interconnect performance, a low capacitance TSV was designed and was experimentally confirmed that the capacitance was 90 fF/TSV. To enhance the performance, an adaptive timing control was applied to a low voltage swing circuit. Feeding back information on the TSV capacitance to an output voltage control as timing signals, difficulties in timing designs resulting from variations of TSV capacitances were resolved. The circuit has scalability to the number of stacked TSVs and a robustness against process-to-process variations of TSV capacitances. The power efficiency of at least 27% is enhanced using the low voltage swing circuit. A data-rate of 1 Tbps/mm2 and the highest power efficiency of 6 Tbps/W were experimentally confirmed using 3D-stacked chips with the low capacitance TSVs.