Akito Sekiya

On-chip test of the shift register for high-end network switch based on cell-based design

We have demonstrated the high-speed operation up to 55 GHz with a bias margin of ±5.5% for a shift register based on the single-flux-quantum logic circuit. The shift register is employed in the rate transfer circuit in high-end network switches that are made up with the cell-based design technique. The on-chip test system was used for measuring the operation frequencies, and the test system itself was built by combining the cells to satisfy the boundary conditions between the test system and the circuit-under-test. As a result, the on-chip test system developed in this study has high flexibility.

Timing Jitter Measurement in Single-Flux-Quantum Circuits Based on Time-to-Digital Converters With High Time-Resolution

We evaluated timing jitter based on a time-to-digital converter (TDC) having sub-pico seconds time resolution. The measured jitter at liquid helium temperature was 65 fs for an optimally damped simple junction composing a conventional Josephson transmission line fabricated with the NEC standard process. The temperature dependence and shunt resistance dependence of jitter indicate that the jitter originates from thermal noise generated at the shunt resistor of the junction. We also found that the timing jitter of a balanced comparator is much larger than that of a JTL. The jitter of a balanced comparator is independent of temperature. This means that the jitter of a balanced comparator does not arise from thermal noise.

Demonstration of the multi-bit sigma-delta A/D converter with the decimation filter

We have proposed a multi-bit sigma-delta analog-to-digital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.

Design and demonstration of SFQ pipelined multiplier

We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSAs). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of /spl plusmn/5.5%.

Demonstration of decimation filter and high-speed testing of a component of the filter

We study decimation filters based on the single-flux-quantum circuit in order to realize over-sampled AD converter. We designed the decimation digital filters using CONNECT cells, a well-developed cell library. We designed a T1 cell, because the T1 cell is the key for the counting-type decimation filter. We confirmed correct operation up to 43 GHz by using an on chip test system. Using the T1 cell, we designed second-order counting-type decimation sinc filters with decimation factors N=2 and N=4. The circuit scale was as high as 2758 junctions. We also confirmed the correct operation of these filters.

High-Resolution Analog-to-Digital Converters toward Software-Defined-Radio Receivers

We describe three types of software-defined-radio (SDR) receivers based on superconducting technologies. The superconducting analog bandpass filters are essential for all types of the receivers. Another key component is an analog-to-digital converters (ADCs), which are required to have high resolution with a broad band width. The complementary A ADC based on the single-flux-quantum circuit is a promising candidate for the SDR receivers because it has a practical nature together with above-mentioned requirements. The experimentally obtained signal-to-noise ratio (SNR) and sensitivity, which are closely related to the resolution, are 34 dB and 20 μA for a quarter of the full-scale input with a band width of about 20 MHz. If we use the optimum decimation filter, the ADC is expected to have the SNR of 82 dB and the sensitivity of 300 nA. These values meet the requirements of the easiest type of the SDR receiver. After new fabrication process has been introduced and the architecture of the ADC has been improved, all types of recievers could be realized based on suoerconductors.

Numerical analysis of superconductive oversampling analog-to-digital converters

We have numerically studied oversampling analog-to-digital converters (ADCs) in terms of sensitivity, spurious-free dynamic range, signal-to-noise ratio (SNR) or dynamic range toward the application to a future mobile communication system. These ADCs are based on single-flux-quantum logic. The sensitivity depends on the impedance of the grounded element, while the SNR is less dependent on the architecture of the modulator. A band-pass /spl Sigma/-/spl Delta/ modulator is suitable for digital RF radios due to its high sensitivity. The second-order modulator with a feedback gain of 20 and 50 GHz-operation of the single-loop modulator show the same effect on the improvement of SNR. Further improvement required for the digital RF architecture can be realized by using a multi-bit comparator or by higher operating speed.

Demonstration of the SFQ pipelined circuit at 14 GHz

Abstract We have tested a pipelined SFQ circuit at high clock frequencies using the on-chip test system. The circuit under test (CUT) is a half adder (HA), which has the structure of a two-stage pipeline. To simplify the on-chip test system, a two bit-shift register (SR) is added to the HA. This SR has a “Data-Out” terminal and a “Tap-Out” terminal, which are connected to the two “Input” terminals of the HA. This structure reduces the number of the input terminals of the CUT to one terminal and is regarded as one of the basic component of the digital filter. We have confirmed that the CUT operates correctly with wide bias margins up to 14 GHz.