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Featured researches published by Akira Asato.


international solid-state circuits conference | 1999

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism

Hajime Kubosawa; Naoshi Higaki; Satoshi Ando; Hiromasa Takahashi; Yoshimi Asada; Hideaki Anbutsu; Tomio Sato; Masato Sakate; Atsuhiro Suga; Michihide Kimura; Hideo Miyake; Hiroshi Okano; Akira Asato; Yasunori Kimura; Hiroshi Nakayama; Masayoshi Kimoto; Katsuji Hirochi; Hideki Saito; Norio Kaido; Yukihiro Nakagawa; T. Shimada

A 4-way VLIW geometry processor runs at 312 MHz and contains a PCI/AGP bus bridge in a three-layer-metal CMOS process with 0.21 /spl mu/m design rules at 2.5 V. It features: (1) VLIW and SIMD instruction sets, (2) a software bypass mechanism, (3) special condition-code registers and branch condition generator for clipping, and (4) automatic clock delay tuning. The result is performance of 2.5 GFLOPS and 6.5 Mpolygons/s in a 3D geometry processor. This chip can be added to conventional graphics systems without requiring additional LSIs.


international solid-state circuits conference | 1998

A 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

Hajime Kubosawa; Hiromasa Takahashi; Satoshi Ando; Yoshimi Asada; Akira Asato; Atsuhiro Suga; Michihide Kimura; Naoshi Higaki; Hideo Miyake; Tomio Sato; Hideaki Anbutsu; Toshitaka Tsuda; Tetsuo Yoshimura; Isao Amano; Mutsuaki Kai; Shin Mitarai

A microprocessor with single instruction multiple data stream (SIMD) architecture and as many as 170 media instructions for multimedia embedded systems meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and 3DCG image processing capabilities, (b) programming flexibility, and (c) low power dissipation and low cost. It also works as a general purpose microprocessor with mid-range performance. The microprocessor uses 0.21 /spl mu/m CMOS technology, and the chip achieves 2.16 GOPS/720 MFLOPS at a 180 MHz operation with 1.2 W dissipation.


Archive | 2010

Examination of Extraction with Vortex Regions in Paranasal Sinus of Human Nose

Sho Hanida; Masahiro Watanabe; Futoshi Mori; Kiyoshi Kumahata; Akira Asato; Shigeru Ishikawa; Teruo Matsuzawa

The nasal cavity has functions which is breathing, smelling, humidification, warming and cleaning of the inhaled air. It is important for human life-sustaining. And nasal cavity has complex anatomy. In this paper, we have examined the flow/vortex in paranasal sinus. Paranasal sinus divides into four parts depend on location, 1) Maxillary Sinuses, 2) Frontal Sinuses, 3) Ethmoidal Sinuses and 4) Spenoid Sinuses. We focus especially Maxillary Sinuses (MS) in this paper. Maxillary Sinuses is an area connected with both sides of both nasal cavities one by one. The examination of the simulation of the nasal cavity that contains the MS is not enough. And, we thought that MS has some influences for flow of nasal cavity. Therefore, we examine flow in nasal cavity that contains MS. In the general, CFD (Computational Fluid Dynamics) simulation results are visualized by general visualization method such as Vector, Stream lines, Particle flow and LIC (Line Integral Convolution). By these techniques, the flow can be abstractly understood. However, the vortex area cannot be clearly visualized. Especially, shape of vortex region is necessary to understand the phenomenon in MS and connected point between nasal cavity and MS. In this paper, we have examined extraction method for airflow as cavity flow. There are some extraction methods of vortex regions, for example, Lambda2, Q-criterion and vorticity magnitude, etc [3]. And we have extracted vortex regions from results of simulation in nasal cavity. In the result, we can see the two vortexes in MS, and we confirmed it was right and left of MS and the result was different. The shape of MS is right and left and slightly different. However, the pattern of the flow became a different clearly.


international conference on e science | 2006

Grid Service Platform: Design and Implementation of Grid Middleware for Telecom Carriers

Soichi Shigeta; Nobutaka Imamura; Haruyasu Ueda; Hiromichi Kobashi; Miho Murata; Taketoshi Yoshida; Atsushi Kubota; Akira Asato; Yoshimasa Kadooka

We have developed the Grid Service Platform (GSP), which is a grid middleware for telecom carriers. GSP can support not only non-interactive batch style services, but also interactive real-time services. Moreover, GSP attains autonomous resource sharing between services based on the priority of each service. We conducted a field trial of GSP on a testbed that consisted of three sites in Japan and France. Two different types of services were implemented on GSP: a video conferencing service (interactive) and a batch queuing service (non-interactive). As a result, the performance of both services were simultaneously enhanced. The session capacity of the video conferencing service was improved by up to 30%, while the total execution time of batch jobs was reduced by 12%.


Archive | 2006

Network management method, program, and system

Yoshiro Ikeda; Akihiro Yasuo; Atsushi Mori; Akira Asato; Katsuhiko Nishikawa


Archive | 2001

Data processing device having a variable length code processing mechanism

Akira Asato


Archive | 1998

Data processing device to compress and decompress VLIW instructions by selectively storing non-branch NOP instructions

Yasushi Iwata; Akira Asato


Archive | 1998

Selecting register or previous instruction result bypass as source operand path based on bypass specifier field in succeeding instruction

Akira Asato


Archive | 1998

Compiling apparatus and method for a VLIW system computer and a recording medium for storing compile execution programs

Yasushi Iwata; Akira Asato


Archive | 2006

Network management method, program and system for constructing a parallel computer system

Yoshiro Ikeda; Akihiro Yasuo; Atsushi Mori; Akira Asato; Katsuhiko Nishikawa

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