Tomio Sato

A 54*54-b regularly structured tree multiplier

A 54-b*54-b parallel multiplier was implemented in 0.88- mu m CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a recurring block which generates seven partial-product bits and compresses them to a pair of bits for the sum and carry signals. This block is used repeatedly to construct an RST block in which even wiring among blocks included in wire shifters is designed as recurring units. By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme. In addition, to design time savings, layout density is increased by 70% to 6400 transistors/mm/sup 2/, and the multiplication time is decreased by 30% to 13 ns. >

Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement

A time-to-digital converter (TDC) utilizing a vernier delay line (VDL) technique has relatively large timing errors when the mismatch of the vernier delay is large. In order to overcome this problem, we propose a technique for compensating the vernier delay mismatch using multiple ring oscillation measurements of VDL. We verified it using an on-die jitter measurement circuit implemented in 90 nm CMOS technology and 0.880 ps timing resolution was obtained experimentally.

An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit

The authors discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented. It uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than for conventional carry select adders. The adder is integrated into an area of 0.41*3.36 mm/sup 2/ achieved by a 0.8- mu m, triple-metal, full-CMOS process. >

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism

A 4-way VLIW geometry processor runs at 312 MHz and contains a PCI/AGP bus bridge in a three-layer-metal CMOS process with 0.21 /spl mu/m design rules at 2.5 V. It features: (1) VLIW and SIMD instruction sets, (2) a software bypass mechanism, (3) special condition-code registers and branch condition generator for clipping, and (4) automatic clock delay tuning. The result is performance of 2.5 GFLOPS and 6.5 Mpolygons/s in a 3D geometry processor. This chip can be added to conventional graphics systems without requiring additional LSIs.

A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations

A full 64-bit floating-point processing unit (FPU) with a long horizontal instruction code for parallel operations without pipeline interlock is described. The FPU is implemented on a 1.0- mu m CMOS chip containing 300 K transistors and operating at 25 MHz. It runs at a peak rate of 50 MFLOPs and a sustained rate of 15.4 MFLOPs. The register-to-register latency of double and single-precision addition, subtraction and multiplication are 120 ns each. The latency of double-precision division is 640 ns and that of square root is 880 ns.<<ETX>>

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications

A real-time on-die noise sensor continuously detects up to 100 noise events per second without disturbing processor operations, using a 400kb/s serial interface. The noise sensor uses histogram counters and variable detection windows. The sensor measures periodic and single-events in real time. The noise sensor is implemented in a 90nm CMOS testchip.

A 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

A microprocessor with single instruction multiple data stream (SIMD) architecture and as many as 170 media instructions for multimedia embedded systems meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and 3DCG image processing capabilities, (b) programming flexibility, and (c) low power dissipation and low cost. It also works as a general purpose microprocessor with mid-range performance. The microprocessor uses 0.21 /spl mu/m CMOS technology, and the chip achieves 2.16 GOPS/720 MFLOPS at a 180 MHz operation with 1.2 W dissipation.

An 8.5-ns 112-bit transmission gate adder with a conflict-free bypass circuit

In this paper, we describe a 112-bit transmission gate adder utilizing a new bypass circuit control scheme to improve performance. The estimated propagation delay time is 8.5 ns and the number of transistors is 6,941, both of which are smaller than those of conventional carry select adders (CSA). The adder is integrated in an area of 0.41 x 3.36 mm/sup 2/ with a density of 5,476 transistors/mm2 achieved by 0. 8-/spl mu/m CMOS technology.

A 64-bit floating point processing unit for a RISC microprocessor

Describes architecture, layout, and simulation methodology of a high performance 64-bit floating point processing unit (FPU) which is applicable to a RISC microprocessor. The FPU contains a floating point execution unit and a floating point controller for the SPARC S-25 microprocessor. The FPU supports SPARC floating point instructions based on the IEEE Standard for Binary Floating Point Arithmetic (ANSI/IEEE std. 754-1985). Operating frequency is 25 MHz and peak floating point computing performance is 12.5 MFLOPS when it is used with the S-25 SPARC microprocessor. The chip was designed using 0.8 mu m CMOS standard cell technology. The chip size is 16.4*16.4 mm and packaged into 179-pin PGA. Total transistor count was approximately 330000.<<ETX>>