Hajime Kubosawa

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism

A 4-way VLIW geometry processor runs at 312 MHz and contains a PCI/AGP bus bridge in a three-layer-metal CMOS process with 0.21 /spl mu/m design rules at 2.5 V. It features: (1) VLIW and SIMD instruction sets, (2) a software bypass mechanism, (3) special condition-code registers and branch condition generator for clipping, and (4) automatic clock delay tuning. The result is performance of 2.5 GFLOPS and 6.5 Mpolygons/s in a 3D geometry processor. This chip can be added to conventional graphics systems without requiring additional LSIs.

A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations

A full 64-bit floating-point processing unit (FPU) with a long horizontal instruction code for parallel operations without pipeline interlock is described. The FPU is implemented on a 1.0- mu m CMOS chip containing 300 K transistors and operating at 25 MHz. It runs at a peak rate of 50 MFLOPs and a sustained rate of 15.4 MFLOPs. The register-to-register latency of double and single-precision addition, subtraction and multiplication are 120 ns each. The latency of double-precision division is 640 ns and that of square root is 880 ns.<<ETX>>

A 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

A microprocessor with single instruction multiple data stream (SIMD) architecture and as many as 170 media instructions for multimedia embedded systems meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and 3DCG image processing capabilities, (b) programming flexibility, and (c) low power dissipation and low cost. It also works as a general purpose microprocessor with mid-range performance. The microprocessor uses 0.21 /spl mu/m CMOS technology, and the chip achieves 2.16 GOPS/720 MFLOPS at a 180 MHz operation with 1.2 W dissipation.

A 64-bit floating point processing unit for a RISC microprocessor

Describes architecture, layout, and simulation methodology of a high performance 64-bit floating point processing unit (FPU) which is applicable to a RISC microprocessor. The FPU contains a floating point execution unit and a floating point controller for the SPARC S-25 microprocessor. The FPU supports SPARC floating point instructions based on the IEEE Standard for Binary Floating Point Arithmetic (ANSI/IEEE std. 754-1985). Operating frequency is 25 MHz and peak floating point computing performance is 12.5 MFLOPS when it is used with the S-25 SPARC microprocessor. The chip was designed using 0.8 mu m CMOS standard cell technology. The chip size is 16.4*16.4 mm and packaged into 179-pin PGA. Total transistor count was approximately 330000.<<ETX>>