Akira Sudo

Buried bit-line cell for 64 Mb DRAMs

The authors propose a buried bit-line (BBL) stacked capacitor cell structure for high-density dynamic random access memories (DRAMs). The cell area can be reduced to as small as 8.7<e1>F</e1>², where <e1>F</e1> is the lithographic feature size. A 2.25-&mu;m² cell area is achieved using a 0.51-&mu;m feature size. A 1.4-&mu;m² cell area is attainable using a 0.4-&mu;m feature size. The memory-cell vertical size (2<e1>F</e1>) includes a line and space for a trench isolation pattern in which the buried bit-line is formed. The horizontal size (4<e1>F</e1>+<e1>a</e1>) includes two word-line line and space pairs and a word-line to bit-line contact alignment tolerance denoted by <e1>a</e1>. A storage node contact is self-aligned to the word-line. Since the <e1>a</e1> is considered to be less than <e1>F</e1>/2, a cell area of less than 9<e1>F</e1>² is realized. If the bit-line contact is also self-aligned to the word-line, an 8<e1>F</e1>² cell area can in theory be realized