Yusuke Kohyama

Buried bit-line cell for 64 Mb DRAMs

The authors propose a buried bit-line (BBL) stacked capacitor cell structure for high-density dynamic random access memories (DRAMs). The cell area can be reduced to as small as 8.7<e1>F</e1>², where <e1>F</e1> is the lithographic feature size. A 2.25-&mu;m² cell area is achieved using a 0.51-&mu;m feature size. A 1.4-&mu;m² cell area is attainable using a 0.4-&mu;m feature size. The memory-cell vertical size (2<e1>F</e1>) includes a line and space for a trench isolation pattern in which the buried bit-line is formed. The horizontal size (4<e1>F</e1>+<e1>a</e1>) includes two word-line line and space pairs and a word-line to bit-line contact alignment tolerance denoted by <e1>a</e1>. A storage node contact is self-aligned to the word-line. Since the <e1>a</e1> is considered to be less than <e1>F</e1>/2, a cell area of less than 9<e1>F</e1>² is realized. If the bit-line contact is also self-aligned to the word-line, an 8<e1>F</e1>² cell area can in theory be realized

A 0.15 /spl mu/m KrF lithography for 1 Gb DRAM product using highly printable patterns and thin resist process

In order to realize the 1 Gbit DRAM product, 0.15 /spl mu/m photolithography will be necessary. Recently, off-axis illuminations and phase shift masks have been studied for realizing 0.175-0.25 /spl mu/m lithography. Even if these technologies are used, 0.15 /spl mu/m lithography is difficult. Investigating various lithographic approaches by optical simulation including the effect of photoresist processing, we found that a thin resist (300 nm thick), highly printable memory cell patterns, and optical proximity correction are very useful for realizing the 0.15 /spl mu/m rule DRAMs with KrF laser stepper (NA=0.6).

Future directions for DRAM memory cell technology

The development trend and concerns of cell technologies are reviewed, and future actions for DRAM cell and process module are discussed. The BEST cell and the BST cell are promising for giga bit era DRAM. The BEST cell has simple and robust processes, and the conventional capacitor dielectric film is available. The BST film development is the key to realizing giga bit era DRAM by using BST cell.

Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

Integration technology of low resistance word line and scaled CMOSFETs for 1 Gbit DRAMs and beyond is proposed. Polymetal (W/WSiN/Poly-Si) word lines and dual gate CMOS FETs with oxynitride gate dielectric were introduced to the 8F/sup 2/ DRAM cell technology. Low sheet resistance of 4.5 /spl Omega///spl square/ word line with 40 nm thick W and high performance dual gate 0.18 /spl mu/m CMOS were successfully integrated without any constraint.

Control of Two Types of Dielectric Relaxation Current for Ta2O5 Metal-Insulator-Metal Capacitors

Ta2O5 is the most promising high-k dielectric candidate for metal-insulator-metal (MIM) capacitors, but its dielectric relaxation (DR) currents may cause irrecoverable charge loss, although DR is a universal phenomenon of normal dielectrics. Therefore, the Ta2O5 MIM capacitors DR chasracteristics and their control were investigated. Ta2O5 DR is composed of two components. One component shows t-1-type time decay, which is assumed to be caused by nonuniformity of electron polarization and is almost of the same order as that of SiN. Thus, its influence on dynamic random access memory (DRAM) operation will be limited. The other component shows t-0.5-type time decay, which is caused by hydrogen deoxidation of Ta2O5, and is dominant in the case of deoxidized Ta2O5 DR. It causes about 16% charge loss. Namely, it will have an adverse influence on DRAM operation. N2 annealing is a possible solution for the reduction of this t-0.5-type DR.

Level-specific strategy of KrF microlithography for 130 nm DRAMs

This paper reports technologies that enable KrF microlithography to be extended to 130 nm generation devices. Firstly, focus and dose budget analyses are carried out carefully to estimate their total deviations. Secondly, level specific cell-array patterns and exposure conditions are optimized for obtaining more process windows than the deviations by experiment and simulation. Optical proximity effect (OPE) and process proximity effect (PPE) for each level are investigated for core and peripheral circuit patterns. The key technologies for KrF microlithography, i.e. resolution enhancement technologies (RET) and process proximity correction (PPC), are discussed with a view to realizing 130 nm DRAMs.

Boron diffusion layer formation using Ge cryogenic implantation with low-temperature microwave annealing

It is shown that a low-sheet-resistance p-type diffusion layer with a small diffusion depth can be fabricated efficiently by cryogenic boron and germanium implantation combined with low-temperature (400 °C) microwave annealing. Compared with the conventional annealing at 1000 °C, a much smaller diffusion depth is obtained at the same sheet resistance. The low sheet resistance at 400 °C is due to microwave absorption in the surface amorphous layer, which is formed by cryogenic germanium implantation. However, the pn junction leakage was worse than that in conventional annealing, because crystal defects remain near the amorphous/crystal interface after microwave annealing. It is found that the pn junction leakage is improved greatly by cryogenic germanium implantation. These results show that a suitable combination of cryogenic implantation and microwave annealing is very promising for p-type diffusion layer technology.

Liner-supported cylinder (LSC) technology to realize Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAMs

The concept of liner-supported cylinder (LSC) technology to realize robust formation of cylindrical electrodes with Ru, which has advantages to bring out the best of Ta/sub 2/O/sub 5/ performance, is described. With experimental results including DRAM functionality, we show that LSC-Ta/sub 2/O/sub 5/ capacitor is a promising candidate to realize 0.10 /spl mu/m DRAMs and beyond.

In-situ multi-step (IMS) CVD process of (Ba,Sr)TiO/sub 3/ using hot wall batch type reactor for DRAM capacitor dielectrics

We developed a new in-situ multi-step (IMS) process technology to achieve both conformal step coverage and high dielectric constant for CVD-BST. IMS is a sequential repetition of low temperature CVD of BST and its crystallization in a batch type hot wall reactor that enables uniform BST deposition over 200 mm wafers. Conformal growth of local epitaxially grown BST with a dielectric constant of more than 300 is attained by IMS combined with SrRuO/sub 3/ electrodes.

Low temperature (Ba,Sr)TiO/sub 3/ capacitor process integration (LTB) technology for gigabit scaled DRAMs

Low temperature (600/spl deg/C) (Ba,Sr)TiO/sub 3/ (BST) capacitor process integration (LTB) based on a SrRuO/sub 3/ (SRO) electrode is proposed to achieve gigabit scaled and embedded DRAMs. The BST crystallization temperature is successfully reduced by SRO, which has the same perovskite structure as the BST film. Chemical Mechanical Polishing (CMP) and O/sub 3/ water etching are developed for storage node (SN) electrode and plate (PL) electrode patterning. A new low temperature post anneal method is also proposed in order to reduce oxygen vacancies at the top electrode-BST interface.