Akram Salman

ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-/spl mu/m CMOS technology

Historically, the failure mode of the nMOS/lateral n-p-n (L/sub npn/) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-/spl mu/m CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by I/sub D/-V/sub G/ and I/sub G/-V/sub G/ measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current I/sub f/ of the nMOS/L/sub npn/ are studied, and it is shown that as the device ages from an oxide perspective, its ESD protection capabilities decrease.

Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design

Bulk pseudo-nMOS (i.e. CMOS with grounded pMOS pullup device) circuits have been quite popular in the past because they are fast, small and pMOS devices are good pullup resistive loads. A pseudo-nMOS gate with a fan-in of N requires only N+1 transistors (as opposed to 2N for standard CMOS), resulting in smaller area as well as smaller parasitic capacitances, whereas each input connects to only one transistor, presenting a smaller load to the preceding gate. Since these advantages come at the expense of static power consumption, pseudo-nMOS circuits have often lost their appeal for large circuits, even though they are frequently used in some critical path elements when speed and area are at a premium (Weste and Eshraghian, 1993). If a weaker pMOS load transistor could be used without sacrificing speed, for example by reducing the load on the dotted node (either due to smaller devices in the pulldown tree, or to a smaller driven load representing a similar gate), the static power could be minimized. Since from a circuit designers perspective, one of the major advantages of SOI technology is the reduction of junction capacitance, this paper takes a fresh look at pseudo-nMOS and finds that SOI technology makes possible important performance (speed and power) and area improvements and predicts that it can be used widely in the design of SOI custom-integrated circuits.

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-/spl mu/m CMOS technology

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L/sub npn/ protection devices in a 0.13-/spl mu/m CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 /spl mu/m) devices fail because of source/drain filamentation, whereas longer (0.3 /spl mu/m) devices with thin (22 /spl Aring/) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I/sub t2/. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device.

Evaluation of ESD characteristics for 65 nm SOI technology

With aggressive scaling and continuous drive for higher performance requirements, electrostatic discharge is becoming a major reliability challenge for advanced integrated circuits. Products must be designed with proper ESD protection circuits to provide adequate robustness and as the limits of the device capability are reached, factors like device reliability due to ESD sensitivity became more critical. In this paper, the ESD characteristics of I/O elements in 65nm SOI technology are thoroughly evaluated. With an appropriate design implementation using these discrete elements, industry standard ESD robustness can be achieved.

Electrostatic discharge induced oxide breakdown characterization in a 0.1 /spl mu/m CMOS technology

Historically, the failure mode of the NMOS/lateral NPN (Lnpn) due to electrostatic discharge (ESD) is source-to-drain filamentation as the temperature exceeds the melting temperature of silicon. However, as the oxide thickness shrinks, the ESD failure is instead due to oxide breakdown. In this paper, transmission line pulse (TLP) testing of the NMOS/Lnpn device is used to characterize the failure mode for a 0.1 /spl mu/m NMOS. The channel length and non-silicided source contact-to-gate spacing (SCG) are the main parameters in determining ESD protection capability. Using Id-Vg measurements, we show how oxide degradation before failure is detected with the leakage current failure criteria used. The latent effects of oxide degradation on the second breakdown current (It2) of the NMOS/Lnpn are identified. As the ultra-thin oxide (15 A) device ages from an oxide perspective, its ESD protection capabilities decrease.

Modeling the gated-diode response of an irradiated SOI back-channel interface

In this work the gated-diode technique has been applied to n-channel SOI MOSFETs that were part of a test vehicle used for a 0.25 /spl mu/m SOI CMOS product development. We have shown that the gated-diode technique is a powerful technique for the evaluation of the Si-film/buried-oxide interface, and that the technique is simple in measurement configuration. Our 2D numerical simulation of the SOI back-channel gated-diode results indicates that the back-channel radiation-induced interface state concentration can be modeled as an acceptor interface state at an energy of 0.7eV.

DG-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm LV/LP circuit design

This paper investigates the possibility of using SDG (symmetric double gate) device intrinsically on structure as a load device for DG-SOI based ratioed logic, To establish the feasibility and superiority of this approach an inverter and a NOR gate were designed, which exhibits considerable advantages. The work is then extented to show how the approach can also be used to built NAND and XOR gates to create a complete logic family. All the simulations are done for 50 nm gate length devices using SILVACO tools. Voltage transfer characteristics are studied for both SDG load and ADG (asymmetric double gate) inverter. The transient characteristics obtained with a 1.25 GHz pulse on the n/sup +/-poly gate and a 500 MHz on the p/sup +/-poly gate are also studied.

Device physics considerations for SOI domino circuit design

The ongoing need to increase the speed in tandem with decrease in power consumption has necessitated for an alternative viable technology. Due to device physics and structural properties (i.e., reduced junction capacitance, higher driving current etc) and limited technology transfer, Partially-Depleted (PD) SOI technology has become the de-facto candidate for replacing Bulk CMOS technology. It has matured to an extent that it can now be implemented in most of the applications. This paper explains how design parameters for pseudo n-MOS can be changed to maximize the advantage of SOI technology. Further, we extend this idea to dynamic logic circuits and evaluate its viability.

“Gated-diode” configuration in SOI MOSFET’s: A sensitive tool for evaluating the quality and reliability of the buried Si/SiO2 interface

A “gated-diode” configuration in SOI MOSFET’s is described, which is particularly suitable and easy to use for characterizing the buried oxide interface. This new approach becomes possible by taking advantage of the front gate, which is biased to inversion (NMOSFET’s) or accumulation (BC-PMOSFET’s) during the measurement. As a result, the drain merges with the inversion or accumulation layer and “extends” under the entire gate, forming a “horizontal” p-n junction with the channel. The drain-to-body diode is then forward-biased by a small voltage, and the back gate voltage is scanned such that it brings the back interface to depletion, a condition that is at the center of all gated-diode techniques and required to activate the interface states and start the recombination/generation processes. The mid-channel interface state density is obtained from the peak of the measured current vs. back gate voltage curves, and by combining the measurements with 2D numerical simulations (e.g. a combination of SUPREM and...