Dimitris E. Ioannou

Adaptation of the charge pumping technique to gated p-i-n diodes fabricated on silicon on insulator

The charge pumping technique was applied to MOS p-i-n diodes and used to characterize silicon-on-insulator films synthesized by oxygen implantation. The flatband and threshold voltages, effective channel length, capture cross sections, and densities of traps at the front and back interfaces were extracted. The parameters of the charge pumping phenomenon were systematically studied, and the ranges of validity are discussed. A parasitic component, due to an excess recombination of mobile carriers, occurs for very short transients during both the rise and fall of the gate pulse. It is demonstrated that the carrier reservoirs situated at the back interface play a significant role. Other specific features related to the dual-gate operation and interface coupling in silicon-on-insulator films are presented. An improved model is developed for the interpretation of the interface state profile in the energy gap. >

Properties of ultra-thin wafer-bonded silicon-on-insulator MOSFET's

Strong interface coupling effects on the subthreshold and transconductance characteristics have been experimentally observed and analytically modeled. For total depletion, the subthreshold swing reaches a nearly ideal value. The front channel subthreshold slope of ultrathin MOSFETs is very sensitive to the density of states at the buried Si-SiO/sub 2/ interface so that a thicker fully depleted film is preferable when the quality of this interface is poor. The transconductance reaches a maximum for total depletion. Simple theoretical models are proposed which explain the substantial variations of the transconductance and subthreshold slope as the opposite interface is scanned from inversion to total depletion and accumulation. These MOSFETs behave very well and demonstrate that high carrier mobilities and low densities of defects can be obtained at both interfaces even in ultrathin silicon-on-insulator (SOI) structures. >

In depth analysis of opposite channel based charge injection in SOI MOSFETs and related defect creation and annihilation

Abstract Extensive PISCES simulations, incorporating non-local effects are carried out to obtain an in-depth understanding of the recently observed opposite channel based charge injection in SOI MOSFETs [1]. This charge injection is then combined with basic transistor characteristics and charge pumping current measurements to study the hot carrier degradation mechanisms in a variety of SOI MOSFETs, and clarify the separate roles played by hot electrons and holes in the degradation. It is also used as the basis for the design of a new, SOI based flash memory cell.

Hot-electron-induced degradation of front and back channels in partially and fully depleted SIMOX MOSFETs

The characteristics of the front and back channels of 1- mu m-long SIMOX MOSFETs were measured before and after various types of periods of hot-electron stress, and a comparison between the induced degradations was made. The back channel degrades much more severely than the front channel for both partially depleted and fully depleted devices. Fully depleted MOSFETs (140-nm-thick) are favorably contrasted with partially depleted ones (300-nm-thick) as to their vulnerability to hot-carrier-induced damage. Although defects are always located at and/or near the interface of the stressed channel, they may influence the properties of the opposite channel (via interface coupling) in fully depleted MOSFETs.<<ETX>>

Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies

In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp

Silicon nanowire on oxide/nitride/oxide for memory application

We report the fabrication and characterization of Si nanowire memory devices with oxide/nitride/oxide stacked layers as the gate dielectrics and charge storage media. The devices were fabricated by using photolithography to pattern the metal contacts to the Si nanowires grown on pre-defined locations. A large memory window with high on/off-state current ratio due to the small radius and intrinsic doping of the Si nanowire is obtained. In addition, the simple reversible write/read/erase operations have been implemented with these memory devices. The dynamics of the nanowire/nitride charge exchange and its effect on the threshold voltage and memory retention have been investigated.

Opposite-channel-based injection of hot-carriers in SOI MOSFET's: physics and applications

An extensive study of the recently observed opposite-channel-based injection (OCBI) of hot-carriers in SOI MOSFETs is carried out by PISCES numerical calculations. The study reveals similar patterns of injection for partially-depleted (PD) and fully-depleted (FD) devices, although there are significant quantitative differences. Important differences also exist when stressing the device with the body floating versus body grounded. The results demonstrate that when stressing one channel, carriers can and are injected into the opposite gate. The results also demonstrate that under appropriate bias conditions pure electron/hole injection takes place, and establish these conditions. The practical significance of this ability to inject only electrons or only holes in any desired sequence is illustrated by exploiting it to investigate the time-power law of interface state generation and to design a SOI EEPROM cell with a back channel based erasing scheme.

Influence of Metal–MoS2 Interface on MoS2 Transistor Performance: Comparison of Ag and Ti Contacts

In this work, we compare the electrical characteristics of MoS2 field-effect transistors (FETs) with Ag source/drain contacts with those with Ti and demonstrate that the metal-MoS2 interface is crucial to the device performance. MoS2 FETs with Ag contacts show more than 60 times higher ON-state current than those with Ti contacts. In order to better understand the mechanism of the better performance with Ag contacts, 5 nm Au/5 nm Ag (contact layer) or 5 nm Au/5 nm Ti film was deposited onto MoS2 monolayers and few layers, and the topography of metal films was characterized using scanning electron microscopy and atomic force microscopy. The surface morphology shows that, while there exist pinholes in Au/Ti film on MoS2, Au/Ag forms a smoother and denser film. Raman spectroscopy was carried out to investigate the metal-MoS2 interface. The Raman spectra from MoS2 covered with Au/Ag or Au/Ti film reveal that Ag or Ti is in direct contact with MoS2. Our findings show that the smoother and denser Au/Ag contacts lead to higher carrier transport efficiency.

Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO(2) charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO(2) increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO(2) thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.

Surface potential at threshold in thin-film SOI MOSFET's

The usual condition for threshold in bulk MOSFETs, of equal rates of change with gate voltage of the inversion and bulk charges, is suitably modified to describe threshold in fully depleted SOI MOSFETs. Using this modified condition the value of the surface potential at threshold in fully depleted transistors is obtained analytically in terms of device dimensions, film doping level, and applied voltages. The results are in excellent agreement with one-dimensional numerical simulations, and it is shown that the surface potential at threshold may differ significantly from 2 phi /sub F/, the value conventionally assumed. >